Verilog Language

P
What's the best book on the verilog RTL synthesizable subset
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1
Views
737
VhdlCohen
V
D
Problem with Modelsim Lisence server...
Replies
3
Views
828
Prasanna
P
M
generate a 20 MHZ clock(pulse) with duty cycle other than 50
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2
Views
844
Prasanna
P
R
syntax question
Replies
2
Views
811
Steven Sharp
S
J
Data Structure Viewer
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2
Views
1K
Arvind Kumar
A
C
custom memory array implementaion
Replies
2
Views
799
Jim Wu
J
P
What's the difference between PrimePower, Power Compiler and
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0
Views
489
Peng Yu
P
A
state machine interaction with a xilinx block ram
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0
Views
334
alison
A
P
How to Instantiate RAM & ROM using Verilog HDL in Behavioral
Replies
5
Views
1K
Chris Briggs
C
R
Verification Intern Positions Available
Replies
0
Views
380
Recruit Interns
R
P
How to write a netlist in Behavioral Compiler for HSPICE?
Replies
0
Views
436
Peng Yu
P
A
Vim syntax file for Verilog 2000
Replies
0
Views
471
Allan Herriman
A
P
What's the differences between translation_* and synthesis_*
Replies
2
Views
888
Peng Yu
P
D
Nested generate statement problems
Replies
1
Views
681
Jonathan Bromley
J
C
Earn $500 to $700 per Week Downloading FREE Software 9xg
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0
Views
454
Cash Cow
C
P
nc-verilog: illegal concatenation error
Replies
4
Views
1K
xno
X
W
is there a way to do file I/O during simulation using Verilo
Replies
3
Views
838
Andy Peters
A
C
OT: flexlm license tracking
Replies
3
Views
1K
Prasanna
P
C
help link_library in synopsys
Replies
1
Views
706
Alan Fitch
A
W
which book is best for studying Verilog with meaningful exam
Replies
0
Views
452
walala
W
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