Verilog Language

W
how to design this datapath unit for DSP using VHDL/Verilog?
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0
Views
468
walala
W
E
a 50/50 clock divider
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0
Views
439
Eng Gan
E
A
Initializing counters in Verilog
Replies
4
Views
998
John_H
J
L
how to use random in verilog
Replies
2
Views
1K
Swapnajit Mittra
S
C
bus analyzer(hardware + front-end software) versus bus check
Replies
2
Views
822
Andrew Paule
A
A
Question about Assignment of a one-dimensional array to a tw
Replies
1
Views
710
Steven Sharp
S
A
Poor man's prototyping of some ASIC designs.
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0
Views
490
Arnold Z.
A
A
Avoiding races in verification code
Replies
4
Views
829
a2zasics
A
J
Forcing a value into multi-dimensional array (ModelSim)
Replies
0
Views
451
Jean-Christophe Rat
J
C
bus analyzer(hardware + front-end software) versus bus check
Replies
0
Views
445
Cute Panda
C
B
LONG DISTANCE FOR 3.85 CENTS A MINUTE, NO MONTHLY FEE, NO 10
Replies
0
Views
425
Bill
B
R
Array of reals?
Replies
1
Views
938
Steven Sharp
S
H
Accessing Simulator Event Queue!
Replies
1
Views
950
Swapnajit Mittra
S
S
Concat on RHS of for-loop incrementer?
Replies
1
Views
713
Steven Sharp
S
P
Passing signals across different voltages...
Replies
0
Views
440
Prasanna
P
Q
C++ Template Classes of Multi-Value Logic
Replies
6
Views
1K
Renaud Pacalet
R
P
PLI system functions, size checking, return values and simul
Replies
3
Views
910
Michael Neilly
M
S
parameters for Routability estimation and analysis during RT
Replies
1
Views
681
Mike Treseler
M
I
call for papers
Replies
0
Views
556
INFO
I
C
Is transaction-based debugging useful ?
Replies
7
Views
1K
Alexander Gnusin
A
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