Verilog Language

W
is there any books/online resources talking about DSP design
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0
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496
walala
W
W
how to design this datapath unit for DSP using VHDL/Verilog?
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0
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532
walala
W
E
a 50/50 clock divider
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0
Views
503
Eng Gan
E
A
Initializing counters in Verilog
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4
Views
1K
John_H
J
L
how to use random in verilog
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2
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1K
Swapnajit Mittra
S
C
bus analyzer(hardware + front-end software) versus bus check
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2
Views
894
Andrew Paule
A
A
Question about Assignment of a one-dimensional array to a tw
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1
Views
776
Steven Sharp
S
A
Poor man's prototyping of some ASIC designs.
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0
Views
565
Arnold Z.
A
A
Avoiding races in verification code
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4
Views
910
a2zasics
A
J
Forcing a value into multi-dimensional array (ModelSim)
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0
Views
508
Jean-Christophe Rat
J
C
bus analyzer(hardware + front-end software) versus bus check
Replies
0
Views
496
Cute Panda
C
B
LONG DISTANCE FOR 3.85 CENTS A MINUTE, NO MONTHLY FEE, NO 10
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0
Views
498
Bill
B
R
Array of reals?
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1
Views
1K
Steven Sharp
S
H
Accessing Simulator Event Queue!
Replies
1
Views
1K
Swapnajit Mittra
S
S
Concat on RHS of for-loop incrementer?
Replies
1
Views
781
Steven Sharp
S
P
Passing signals across different voltages...
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0
Views
499
Prasanna
P
Q
C++ Template Classes of Multi-Value Logic
Replies
6
Views
1K
Renaud Pacalet
R
P
PLI system functions, size checking, return values and simul
Replies
3
Views
1K
Michael Neilly
M
S
parameters for Routability estimation and analysis during RT
Replies
1
Views
751
Mike Treseler
M
I
call for papers
Replies
0
Views
654
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