Verilog Language

W
IC area for a flip-flop and SRAM?
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1
Views
761
Jason Hu
J
S
RTL power estimation
Replies
1
Views
673
Petter Gustad
P
J
Bangalore, India -- SoC Wireless Design Manager - Verilog H
Replies
2
Views
705
Petter Gustad
P
M
I need BOOTH MULTIPLIER LOGIC CIRCUIT DIAGRAM....
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0
Views
537
malik tj
M
D
Repeat concatenation and Modelsim
Replies
8
Views
853
Stephen Williams
S
U
If you needed a book on verilog?
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2
Views
703
UJMi
U
D
Must function returns be of a known size?
Replies
9
Views
774
David Wooff
D
J
Bangalore, India -- VLSI/ASIC/CAD Tech Lead, Parasitic Extra
Replies
1
Views
619
me tew!
M
J
Simple PS/2 Keyboard
Replies
7
Views
1K
John
J
S
How to random generate packet for Ethernet MAC(802.3) with v
Replies
0
Views
228
sarah
S
S
How to random generate packet for Ethernet MAC(802.3) with v
Replies
0
Views
469
sarah
S
S
Power estimation
Replies
0
Views
225
Sathyanarayan B
S
S
Power estimation
Replies
0
Views
455
Sathyanarayan B
S
P
Back Annotating encrypted netlists
Replies
0
Views
232
Paul Richardson
P
P
Back Annotating encrypted netlists
Replies
0
Views
451
Paul Richardson
P
J
Interpreting 1364.1-2002 5.2.2.1: Edge FF's with async jam l
Replies
3
Views
687
David Jones
D
J
Interpreting 1364.1-2002 5.2.2.1: Edge FF's with async jam l
Replies
3
Views
820
David Jones
D
D
Ling Adder
Replies
0
Views
509
David
D
P
Enhanced VCD file!!
Replies
2
Views
2K
Anthony J Bybell
A
J
Bangalore, India -- SoC Wireless Design Manager - Verilog H
Replies
0
Views
221
Jerry Bires
J
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