Verilog Language

L
How to write a good verilog code that can be synthesized as
Replies
5
Views
640
Chris F Clark
C
D
Procedural assignment
Replies
3
Views
554
David Wooff
D
A
Defines for Submodules
Replies
3
Views
819
Steven Sharp
S
Z
ending vhdl simulation
Replies
1
Views
604
Stefan Frank
S
N
verilog model of serial presence-detect
Replies
0
Views
230
Nahum Barnea
N
W
IC area for a flip-flop and SRAM?
Replies
1
Views
714
Nahum Barnea
N
T
vcd file size reduction
Replies
5
Views
662
Nahum Barnea
N
D
Where to insert pipeline delays
Replies
2
Views
556
Marko
M
H
IDE/ATA _device_ core availablility
Replies
1
Views
614
Dave Vanden Bout
D
U
If you needed a book on verilog?
Replies
3
Views
587
UJMi
U
K
Nested conditional operation in design compiler
Replies
1
Views
526
John_H
J
R
MAPLD 2004: Registration Open and Program Announced
Replies
0
Views
235
Richard B. Katz
R
M
I need BOOTH MULTIPLIER LOGIC CIRCUIT DIAGRAM....
Replies
1
Views
593
UJMi
U
D
Must function returns be of a known size?
Replies
8
Views
676
Steven Sharp
S
M
Voltage controlled capcitance model
Replies
0
Views
224
Mircea Gindila
M
D
Repeat concatenation and Modelsim
Replies
8
Views
748
Steven Sharp
S
J
Simple PS/2 Keyboard
Replies
5
Views
785
Jeremy Webb
J
D
For help-verilog design of a calculator
Replies
2
Views
661
davidbarby
D
S
Power estimation
Replies
0
Views
464
Sathyanarayan B
S
S
RTL power estimation
Replies
1
Views
551
Petter Gustad
P
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