Verilog Language

C
Need help : proc_i = vpi_iterate(vpiProcess, mod_h);
Replies
2
Views
453
fpgabuilder
F
M
linking pli with NC
Replies
4
Views
3K
David Roberts
D
N
segmentation fault - code attached
Replies
1
Views
510
Narendran Kumaraguru Nath
N
D
parameterized mux issue
Replies
3
Views
740
John_H
J
D
accessing 2D arrays in Verilog
Replies
3
Views
1K
John_H
J
L
RTL behavioural newby questions
Replies
1
Views
498
Carson Pun
C
W
Can NC_Verilog use PLI modules coded with C AND C++ mixed?
Replies
0
Views
130
WestPort
W
K
PSL pros and cons
Replies
2
Views
687
vhdlcohen
V
B
Query in generating clock
Replies
0
Views
270
batrashish
B
R
Inconsistency With Format Specification with $display and $s
Replies
5
Views
617
Steven Sharp
S
A
Yet again Blocking & Non Blocking
Replies
1
Views
468
John_H
J
M
Multiple WLF in ModelSim
Replies
2
Views
645
Muthu
M
S
xilinx webpack
Replies
0
Views
276
samtee
S
P
NCverilog interface with VERA
Replies
0
Views
143
prav
P
M
please tell me why this inout port assignment isnt working!!
Replies
3
Views
665
mw3382
M
S
Problem using $recordvars/$recordfile under NCverilog
4 5 6
Replies
102
Views
9K
Kim Enkovaara
K
W
Creating a Simple counter in Verilog
Replies
2
Views
830
John_H
J
I
CALL FOR PAPERS, ISQED 2005
Replies
0
Views
145
info
I
I
CALL FOR PAPERS, ISQED 2005
Replies
0
Views
300
info
I
A
Announce: TCLforEDA project is back
Replies
0
Views
150
Alexander Gnusin
A
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