Problem using $recordvars/$recordfile under NCverilog

[John_H]

Xilinx Webpack is concerned with Synthesizable Verilog which is a subset of
Simulatable Verilog.
Since Webpack targets hardware, you have to fit the logic within the
constraints of what the hardware can handle.

While you may consider a reset to be a level sensitive signal, I believe
Verilog treats a non-edge signal in the sensitivity list as "posedge or
negedge" not "pos." Any transition on the signal causes the simulator to
enter the block.

If you had a simple reset, the construct

always @(posedge clock or reset)
if( reset ) Val <= 1'b0;
else Val <= input;

would enter both on the posedge of reset which is what is desired but it
will also enter on the negedge of reset. Since the if(reset) evaluates to
false on the negedge, the Val <= input *will* be performed by the simulator.
To get the proper reset, the entry needs to be *only* on the rising edge, so

always @(posedge clock or posedge reset)
if( reset ) Val <= 1'b0;
else Val <= input;

results in the reset only when the signal asserts (or the posedge clock
comes along while still asserted) but exiting the reset leaves the register
alone.

If you're trying to accomplish more than the simple set/reset, consider how
the hardware *can* implement what you want to do. Is your construct able to
be realized with the existing transistors in your target device?


"papu" <prachar@gmail.com> wrote in message
news:1095955221.060749.137750@k17g2000odb.googlegroups.com...

Hi,

I need to place both edge triggered and level triggered signal in the
sensitibity list in "always @()" statements. Verilog allows it. My
program compiles without any error in Modelsim.

I was trying to synthesize the same in Xlinix webpack, but it
wouldn't let me do it. On its website they have mentioned that both
level triggered and edge triggered aren't allowed. Is there anyway to
get around it or does any other systhesis tool let you do that? Thank
you in advance.

Papu.

 

[don]

turbo18t wrote:

I need a small FPGA to use in a lab at school. It doesn't have to be
fast, have millions of gates or in any way be a high performance
model. It just has to work. In the class we're designing relatively
small ALU's and I want to do it in Verilog and burn it. It has to be
a protoboard with I/O's and a PC interface. My friend suggested the
Xilinx Spartan series. Any help is appreciated. Thanks.

Your friend is probably talking about Xilinx's "Spartan 3 Starter Kit."
Xilinx's online store (www.xilinx.com) sells the complete kit for $99
USD. This is a XC3S200 FPGA mounted on a small board, complete with a
PS/2, VGA, and RS/232 connectors. It even has 1MB of memory (SRAM!)

This is an *excellent* starter board. You get more than enough
programmable gates to do a reasonable school project, and its the lowest
priced *modern* FPGA board you can find. There are 2 things I don't
like about the board... the 'I/O connectors' are female, meaning it's
not convenient to probe signals (on an oscilloscope.) The other
annoyance is the SRAM isn't directly accessible from the JTAG interface.
I.e., there's no easy way to initialize (write) the SRAM.

Xilinx seems to be 'out-of-stock' at the moment, but you could check
www.digilentinc.com (Digilent manufactures these boards for Xilinx.)

Also consider Xess's XSA/50 and XSA/100 boards. They don't give you
as much programmable logic, but the board has more memory (4MB SDRAM),
and a full featured 'daughtercard' (+$100 USD) with stereo audio
in/out, and a large 'prototype' area (breadboard) for wiring your
own circuits. Since you said you're doing a small ALU, and you want
I/Os, the Xess board might be a better choice for you. Xess's
website also has a good # of 'sample designs' (by Xess and
third-parties.) This can really help a novice get started with
some topics (like how to generate a VGA-signal to display on your
monitor!)

 

[Kim Enkovaara]

Muthu wrote:

Hi,
I am using Modelsim for my functional simulation. A test case will run
for 2ms - Simulation time.
Opening the vsim.wlf created for 2ms simulation time is very slow for
analysing it.
So, i am thinking of a 2 WLF files for a test case.
ie., vsim1.wlf --- 0ms -- 1 ms
vsim2.wlf --- 1ms -- 2 ms
How can i do that for a single test case?

You can use the wlfman tool to split the original wlf to several pieces.
Also new Modelsim versions are much faster in reading wlf files (5.8 especially).
I have used few gigabyte sized wlfs without any problems.

--Kim