Verilog Language

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ASIC core question
Replies
1
Views
350
Berty
B
S
Timing check disabling via a *.tfile
Replies
0
Views
254
smkilcoyne
S
M
code problem, HELP !
Replies
1
Views
371
Swapnajit Mittra
S
C
how to generate sdf file in cadence buildgates?
Replies
2
Views
607
m
M
G
Link interessante
Replies
2
Views
593
zonker
Z
M
My Bank account EXPLODED
Replies
0
Views
210
Max4568
M
?
Cube Root in Verilog RTL for Synthesis!
Replies
1
Views
427
Keith
K
?
A free graphical netlist trace and modification tool
Replies
1
Views
335
topgun
T
T
how to implement LUT(look-up table) in Verilog
Replies
2
Views
640
Berty
B
T
Correct use of HDL
Replies
6
Views
655
Taha
T
?
Bug in synplify ?
Replies
1
Views
318
-
?
T
[Newbie] Output pins are stuck at VCC or GND
Replies
2
Views
1K
Mike Lewis
M
T
Problem in linking designs in PrimeTime
Replies
1
Views
2K
topgun
T
B
Black box??
Replies
1
Views
396
Neo
N
D
Synopsys VCS
Replies
1
Views
316
Direbert
D
Y
Using an IP core licensed under the LGPL
2
Replies
38
Views
3K
Byron A Jeff
B
M
IP core supply
Replies
0
Views
161
Minimum
M
N
Question on clever use of parameters
Replies
1
Views
353
Swapnajit Mittra
S
C
Stating Timing Analysis - Timing-Critical Paths & False Path
Replies
2
Views
368
Chloe
C
G
Need some advice about coding techniques...
Replies
1
Views
388
Neo
N
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