Verilog Language

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Fast/low area Sorting hardware.
Replies
5
Views
340
Weng Tianxiang
W
T
Modeling large memories in Verilog
Replies
3
Views
382
Swapnajit Mittra
S
C
Frequency Divider (by 2)
Replies
3
Views
377
Berty
B
D
How to write a barrel shifter in Verilog?
Replies
2
Views
371
HDLGuru
H
X
ĎîÄżFTP
Replies
0
Views
206
Xuefei Bai
X
R
Generating CLK signal using PLI
Replies
1
Views
316
Swapnajit Mittra
S
P
PolyPhase Fir filter?
Replies
2
Views
383
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32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
Replies
3
Views
358
Weng Tianxiang
W
K
Anyone has datasheet for the LCD on a Palm's Tungsten W?
Replies
0
Views
167
Krist Neot
K
M
problem with $recordvars for modelsim
Replies
0
Views
170
molu
M
A
Signal Assertion with non blocking assignment
Replies
7
Views
321
npk
N
B
how to solve the problem in modelsim
Replies
3
Views
411
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?
M
modelsim
Replies
0
Views
194
molu
M
?
SIGDA Web Server Invitation
Replies
0
Views
146
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?
X
ANNOUNCE: X-Tek Releases X-Amin HDL Design/Analysis Suite
Replies
0
Views
166
X-Tek Corporation
X
?
State Machines.. and their efficiency.
Replies
3
Views
321
balor
B
A
Signal Assertion with non blocking assignment
Replies
0
Views
152
apurv
A
R
Creation of .trn directly in Modelsim.
Replies
1
Views
468
Swapnajit Mittra
S
C
Verilog Generation
Replies
2
Views
338
Vinilkant Tejaswi
V
S
ANN: Project VeriPage Update - New articles on SystemVerilog
Replies
1
Views
344
Swapnajit Mittra
S
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