Verilog Language

D
Can anyone explain me this code...
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5
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399
ajjc
A
M
In a function, how to I do bit-extension on temp variables:
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1
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389
Rob Dekker
R
J
Generate statements for I/O list
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5
Views
498
John_H
J
T
simulation of bus cycles
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1
Views
363
RobJ
R
M
how to write tri-state bus in rtl
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2
Views
412
mynewlifever@yahoo.com.cn
M
N
Divide-by-14 in Xilinx Spartan FPGA's
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6
Views
482
John_H
J
N
Xilinx "This design element is inferred rather than instanti
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3
Views
343
General Schvantzkoph
G
V
VCS compile Error
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3
Views
460
Petter Gustad
P
S
[ANN] Ruby-VPI 0.8
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0
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106
Suraj N. Kurapati
S
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eeNewsFeed.com BETA testers invited!
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0
Views
96
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STOP what you’re doing - It doesn’t work! V8QW
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0
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134
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STOP what you’re doing - It doesn’t work! J2I8
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0
Views
131
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SPI -- in Verilog ????...Help
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2
Views
537
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H
ROM in verilog
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2
Views
409
Henry
H
A
74xx series TTL library avaliable?
Replies
6
Views
569
Andy
A
?
making OS calls from w/in the simulator
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5
Views
415
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assertions
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6
Views
786
Alex
A
S
[ANN] Ruby-VPI 0.7
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0
Views
109
Suraj N. Kurapati
S
S
assertion
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1
Views
449
Ajeetha
A
?
New Book: A Pragmatic Approach to VMM Adoption // for TB des
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0
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152
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