Verilog Language

P
Any answers on what should be the consistent behavior here
Replies
3
Views
482
parag_paul@hotmail.com
P
?
how to use define in a string?
Replies
4
Views
406
Chris Briggs
C
S
which commercial HDL-Simulator for FPGA?
2
Replies
38
Views
1K
Stephen Williams
S
V
LinkedIn Group For FPGA & CPLD
Replies
0
Views
101
Vikash
V
S
Hamming Encoder
Replies
1
Views
401
Shiv
S
T
ANNOUNCE: new version TimingAnalyzer beta0.84 available
Replies
0
Views
104
timinganalyzer
T
T
ANNOUNCE: new version beta0.84 available
Replies
0
Views
104
timinganalyzer
T
S
FSM
Replies
3
Views
388
Pinhas
P
?
State machine behavior question
Replies
3
Views
490
Jonathan Bromley
J
R
expression size
Replies
2
Views
377
Kevin Neilson
K
G
Verilog book for a newbie
Replies
7
Views
603
Kevin Neilson
K
?
Help with Verilog charge strength
Replies
7
Views
586
glen herrmannsfeldt
G
S
which commercial HDL-Simulator for FPGA?
Replies
0
Views
186
SynopsysFPGAexpress
S
O
Beginner needs help...
Replies
5
Views
657
Andy
A
Y
Opening a file with a reg type
Replies
2
Views
349
Yottameter
Y
A
Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
Replies
5
Views
432
ghelbig
G
?
instantiation to reused module
Replies
4
Views
391
-
?
S
SV Assertions workshop on 20th June , San Jose
Replies
0
Views
102
SVTII
S
P
Is the following type incompatible assignment
Replies
4
Views
449
Jonathan Bromley
J
R
Multiple non-blocking assigns in always block
Replies
4
Views
355
Kevin Neilson
K
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