Verilog Language

L
Signals not seen as used during synthesis
Replies
2
Views
771
laserbeak43
L
U
SPR
Replies
0
Views
127
uche
U
J
Verilog-95 style question
Replies
5
Views
572
Jonathan Bromley
J
M
GNU Lesser Public License and Soft IP
Replies
17
Views
1K
Paul Uiterlinden
P
D
How do I concatenate registers ?
Replies
3
Views
584
Daku
D
A
istantiating an array port referring to individual (or group
Replies
1
Views
487
pallav
P
D
SCLive 3.0 With Verilog, VHDL, SystemC kernels available.
Replies
0
Views
120
dcabanis
D
U
Kenlighten - A social network for knowledge seekers and prov
Replies
0
Views
120
uma kane
U
D
How to access individual bits in registers ?
Replies
6
Views
585
-
?
A
glitch free clock switch for more than two clocks
Replies
1
Views
535
gabor
G
D
C structs in Verilog ?
Replies
2
Views
961
Daku
D
M
Dynamic Power Consumption Estimates/Comparison
Replies
1
Views
462
gabor
G
V
Announcing Nov'11 FPGACamp, Silicon Valley. "Debugging Your
Replies
0
Views
120
Vikram
V
P
DTB
Replies
3
Views
705
Jonathan Bromley
J
P
system verilog null as a literal
Replies
3
Views
574
Jonathan Bromley
J
?
CFP: International Symposium on Memory Management 2010
Replies
0
Views
114
-
?
J
ncelab: *W,SDFINF warning when back annotating SDF
Replies
1
Views
2K
-
?
D
A few Verilog questions
Replies
2
Views
604
gabor
G
K
Port bus order
Replies
3
Views
538
glen herrmannsfeldt
G
P
Is SystemVerilog appropriate for this group?
Replies
1
Views
516
Jonathan Bromley
J
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