Verilog Language

F
A variable index into the generate block
Replies
0
Views
116
fpgabuilder
F
R
<break> is not declared
Replies
4
Views
1K
glen herrmannsfeldt
G
W
Why doesn't this situation generate a latch?
Replies
13
Views
694
Martin Thompson
M
R
shift right arithmetic
Replies
7
Views
627
Cary R.
C
S
SystemVerilog queue initialization using ncverilog +sv?
Replies
1
Views
2K
Jonathan Bromley
J
R
renaming a source file
Replies
1
Views
558
gabor
G
G
Is an inout reg allowed
Replies
4
Views
1K
Nathan Bialke
N
F
SV interface in modules instantiated inside a generate state
Replies
3
Views
840
Jonathan Bromley
J
D
Any Open Source Verilog AMS ?
Replies
0
Views
118
Daku
D
M
Ideas to grab grandparent module name?
Replies
0
Views
112
Mark Curry
M
R
problem with shift left operations
Replies
4
Views
646
glen herrmannsfeldt
G
F
LVDS i/o in a SystemVerilog Interface block
Replies
2
Views
572
fpgabuilder
F
A
SystemVerilog: how to attach an SV interface within a VHDL D
Replies
14
Views
2K
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?
F
expressions in `define
Replies
6
Views
722
fpgabuilder
F
F
initialisation of controller
Replies
6
Views
601
Andy
A
M
Verilog publication/user group?
Replies
3
Views
557
Mark Brehob
M
H
DvCon: Experiencing Checkers for a Cache Controller Design
Replies
0
Views
119
hdlcohen@gmail.com
H
W
How a state machine is constructed using latches?
2
Replies
22
Views
1K
Weng Tianxiang
W
J
Any experienced Icarus users out there?
Replies
5
Views
681
Cary R.
C
S
Parametrisation of a design with interfaces (array of interf
Replies
3
Views
575
Jonathan Bromley
J
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