How a state machine is constructed using latches?

[rickman]

On Feb 24, 9:49 pm, Weng Tianxiang <wtx...@gmail.com> wrote:

      CombReg   <= Comb; <-- lock here by VHDL, not by Lattice

Weng

Who said anything about it be the fault of the tools? I said that it
appeared there was a difference, but then I realized that the async
reset must have priority over the latch enable because it can still be
reset once set up to the point that the value of Comb is captured by
CombReg. Then there is no longer a way to reset the latch.

This is the sort of stuff that makes working with latches difficult.
If the combinatorial logic had been described in the sequential
process, there would have been no possibility of generating a latch.

Rick

 

[Andy]

On Feb 25, 5:49 am, rickman <gnu...@gmail.com> wrote:

If the combinatorial logic had been described in the sequential
process, there would have been no possibility of generating a latch.

Amen!

Andy

 

[Weng Tianxiang]

On Feb 25, 11:34 am, Andy <jonesa...@comcast.net> wrote:

On Feb 25, 5:49 am, rickman <gnu...@gmail.com> wrote:

If the combinatorial logic had been described in the sequential
process, there would have been no possibility of generating a latch.

Amen!

Andy

Rick,
Try this one and there is no lock problem any more in VHDL. See what
happens.

CombProc : process(CombReg, C01, C02)
begin
case CombReg is
when '1' => <-- only change, and not locked again
if (C01 = '1') then
Comb <= '0';
elsif (C02 = '1') then
Comb <= '1';
else
null;
end if;
when others =>
Comb <= '1';
end case;
end process;

Thank you.

Weng