Xilinx

Nah, Lawyers are still top of the list in my book.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
The equation for utilization is very complex. For arithmetic data path however,
I do find
that the Xilinx structure permits a higher density measured in LUTs occupied
when comparing designs
for the same algorithm but optimized for the particular device. This is due
partially
to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so
your arithmetic is
2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has
greatly improved the situation
by adding dedicated gating for doing an adder-subtracter in one level, as well
as logic to permit an
accumulator with load, which are probably the most common use of more than two
input arithmetic.
To be fair, the average user is not going to fully use the Xilinx capability
because the synthesis tools
do not do a great job at inferring more complex structures such as an add/mux or
mux/add etc. In order
to use that, you more or less need to do some very careful coding. Same is true
for taking advantage of
the SRL16s.

The fact of the matter is, I think both vendor's numbers are slanted. Unless
you do the design with the
specific architecture in mind, you are not going to get optimum utilization of
that array. A design that is
optimized for one array is going to generally be a poor fit for another.
Presumably, both vendors have
taken a design or designs that were targetted to their parts, and then ported
those designs to the competition
to come up with these numbers. In both cases, naturally, their device is going
to show superior results
simply because the design database they are drawing upon was optimized to their
parts.

As I've stated many times before, the comparison metric should be a raw count of
the number of 4 LUT/flip-flop
pairs plus a list of additional features with perhaps an equivalent utilization
of that feature if it were not available.
That way, the designer can make an informed decision based on what features he
thinks he will use. In cases
where he doesn't know, the most accurate comparision would be to ignore the
effect of special features altogether,
then accept the gains he gets by using them as gravy.

Paul Leventis wrote:

I might as well give the Altera view -- 12.5% is a gross overstatement of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
that nearly the reverse is true (about a 9% advantage for Stratix). Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you could
see vast density advantages from one architecture or the other.

http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf

If we wanted to, we could start counting our M512 blocks as logic, as they
can be used for shift-registers, small memories, and soft multipliers, but
we don't bother.

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Regards,

Paul Leventis
Altera Corp.

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...
Rick, I will not defend the +12,5%, but I can explain it:

It is the price we all pay for the intense and sometimes ruthless
competition in this market. Without a bloodthirsty competitor "in our
rear-view mirror", we would be gentlemanlike and give you conservative
numbers. But the way it is, our marketing folks think it would throw
away some really (really!) powerful features if they are not somehow
represented in the numbers. Each Xilinx Logic Cell does more than an
Altera LE, there can be no doubt about that.

This is not an excuse (personally I agree with you), but an explanation.

Peter Alfke
==========================

rickman wrote:
I care about the fact that I have to ignore a
column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Ray,

You failed to take into account the many IP cores that are available that are
optimized for a particular architecture.

Examine the vendor's own free IP, for fee IP, and the community around that vendor
for the number of independent or partner vendors of IP.

You don't always have to suddenly create the most complex and highest performing
logic out of thin air (as that is a tough job for the best of us).

And don't forget the many talented consultants that create product specific IP that
beats the performance of the best cores that folks may offer.

But it is true that the more specialized and targeted you get, the less likely it
will port conveniently to any other device, other than the manufacturer that it was
originally on (and not even then if it is a new architecture).

Austin

Ray Andraka wrote:

The equation for utilization is very complex. For arithmetic data path however,
I do find
that the Xilinx structure permits a higher density measured in LUTs occupied
when comparing designs
for the same algorithm but optimized for the particular device. This is due
partially
to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so
your arithmetic is
2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has
greatly improved the situation
by adding dedicated gating for doing an adder-subtracter in one level, as well
as logic to permit an
accumulator with load, which are probably the most common use of more than two
input arithmetic.
To be fair, the average user is not going to fully use the Xilinx capability
because the synthesis tools
do not do a great job at inferring more complex structures such as an add/mux or
mux/add etc. In order
to use that, you more or less need to do some very careful coding. Same is true
for taking advantage of
the SRL16s.

The fact of the matter is, I think both vendor's numbers are slanted. Unless
you do the design with the
specific architecture in mind, you are not going to get optimum utilization of
that array. A design that is
optimized for one array is going to generally be a poor fit for another.
Presumably, both vendors have
taken a design or designs that were targetted to their parts, and then ported
those designs to the competition
to come up with these numbers. In both cases, naturally, their device is going
to show superior results
simply because the design database they are drawing upon was optimized to their
parts.

As I've stated many times before, the comparison metric should be a raw count of
the number of 4 LUT/flip-flop
pairs plus a list of additional features with perhaps an equivalent utilization
of that feature if it were not available.
That way, the designer can make an informed decision based on what features he
thinks he will use. In cases
where he doesn't know, the most accurate comparision would be to ignore the
effect of special features altogether,
then accept the gains he gets by using them as gravy.

Paul Leventis wrote:

I might as well give the Altera view -- 12.5% is a gross overstatement of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
that nearly the reverse is true (about a 9% advantage for Stratix). Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you could
see vast density advantages from one architecture or the other.

http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf

If we wanted to, we could start counting our M512 blocks as logic, as they
can be used for shift-registers, small memories, and soft multipliers, but
we don't bother.

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Regards,

Paul Leventis
Altera Corp.

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...
Rick, I will not defend the +12,5%, but I can explain it:

It is the price we all pay for the intense and sometimes ruthless
competition in this market. Without a bloodthirsty competitor "in our
rear-view mirror", we would be gentlemanlike and give you conservative
numbers. But the way it is, our marketing folks think it would throw
away some really (really!) powerful features if they are not somehow
represented in the numbers. Each Xilinx Logic Cell does more than an
Altera LE, there can be no doubt about that.

This is not an excuse (personally I agree with you), but an explanation.

Peter Alfke
==========================

rickman wrote:
I care about the fact that I have to ignore a
column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Click to expand...
 
Perhaps I missed saying it here. I have stated many times in the past that the best
fit for a particular target is probably going to map pretty poorly to another
architecture. My internal IP is for the most part built up out of primitives to even
get placement optimal.

Austin Lesea wrote:

Ray,

You failed to take into account the many IP cores that are available that are
optimized for a particular architecture.

Examine the vendor's own free IP, for fee IP, and the community around that vendor
for the number of independent or partner vendors of IP.

You don't always have to suddenly create the most complex and highest performing
logic out of thin air (as that is a tough job for the best of us).

And don't forget the many talented consultants that create product specific IP that
beats the performance of the best cores that folks may offer.

But it is true that the more specialized and targeted you get, the less likely it
will port conveniently to any other device, other than the manufacturer that it was
originally on (and not even then if it is a new architecture).

Austin

Ray Andraka wrote:

The equation for utilization is very complex. For arithmetic data path however,
I do find
that the Xilinx structure permits a higher density measured in LUTs occupied
when comparing designs
for the same algorithm but optimized for the particular device. This is due
partially
to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so
your arithmetic is
2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has
greatly improved the situation
by adding dedicated gating for doing an adder-subtracter in one level, as well
as logic to permit an
accumulator with load, which are probably the most common use of more than two
input arithmetic.
To be fair, the average user is not going to fully use the Xilinx capability
because the synthesis tools
do not do a great job at inferring more complex structures such as an add/mux or
mux/add etc. In order
to use that, you more or less need to do some very careful coding. Same is true
for taking advantage of
the SRL16s.

The fact of the matter is, I think both vendor's numbers are slanted. Unless
you do the design with the
specific architecture in mind, you are not going to get optimum utilization of
that array. A design that is
optimized for one array is going to generally be a poor fit for another.
Presumably, both vendors have
taken a design or designs that were targetted to their parts, and then ported
those designs to the competition
to come up with these numbers. In both cases, naturally, their device is going
to show superior results
simply because the design database they are drawing upon was optimized to their
parts.

As I've stated many times before, the comparison metric should be a raw count of
the number of 4 LUT/flip-flop
pairs plus a list of additional features with perhaps an equivalent utilization
of that feature if it were not available.
That way, the designer can make an informed decision based on what features he
thinks he will use. In cases
where he doesn't know, the most accurate comparision would be to ignore the
effect of special features altogether,
then accept the gains he gets by using them as gravy.

Paul Leventis wrote:

I might as well give the Altera view -- 12.5% is a gross overstatement of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
that nearly the reverse is true (about a 9% advantage for Stratix). Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you could
see vast density advantages from one architecture or the other.

http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf

If we wanted to, we could start counting our M512 blocks as logic, as they
can be used for shift-registers, small memories, and soft multipliers, but
we don't bother.

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Regards,

Paul Leventis
Altera Corp.

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...
Rick, I will not defend the +12,5%, but I can explain it:

It is the price we all pay for the intense and sometimes ruthless
competition in this market. Without a bloodthirsty competitor "in our
rear-view mirror", we would be gentlemanlike and give you conservative
numbers. But the way it is, our marketing folks think it would throw
away some really (really!) powerful features if they are not somehow
represented in the numbers. Each Xilinx Logic Cell does more than an
Altera LE, there can be no doubt about that.

This is not an excuse (personally I agree with you), but an explanation.

Peter Alfke
==========================

rickman wrote:
I care about the fact that I have to ignore a
column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
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