Xilinx

[Roberto Gallo]

Hello everyone,

What is the cheapest line of volatile Xilinx´s FPGAs?
What is the relation between Altera´s LEs and Xilinx´s Slices?
I need the cheapest Xilinx FPGA (or from any other manufacturer) that
has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you
suggest?

Thank you very much,
Roberto.

 

[rickman]

Roberto Gallo wrote:

Hello everyone,

What is the cheapest line of volatile Xilinx´s FPGAs?
What is the relation between Altera´s LEs and Xilinx´s Slices?
I need the cheapest Xilinx FPGA (or from any other manufacturer) that
has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you
suggest?

Thank you very much,
Roberto.

If you won't be in production until next year, the cheapest solution
will likely be the Spartan 3. If you need parts now, it would likely be
the Spartan IIE. Both families have about 1500 logic cells in the
smallest part, regardless of what the data sheets says. Xilinx likes to
pad the number since they feel they have "uber-cells" which count as
more than 1 each. But then again, they don't define the term "logic
cell", so I guess they can count them any way they want.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Peter Alfke]

What Altera calls an LE, Xilinx calls a Logic Cell (yes, I know there is
a slight marketing inflation), and two Altera LEs correspond to one
Xilinx slice.
So you are looking for the XC2S30 (the next-to-smallest member) with the
equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents).
Your best bet for low price is the Spartan3 XC3S50 with 1536 LE
equivalents. This chip is available in an early version without BlockRAM.

Peter Alfke, Xilinx Applications
=========================
Roberto Gallo wrote:

Hello everyone,

What is the cheapest line of volatile Xilinx´s FPGAs?
What is the relation between Altera´s LEs and Xilinx´s Slices?
I need the cheapest Xilinx FPGA (or from any other manufacturer) that
has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you
suggest?

Thank you very much,
Roberto.

 

[Peter Alfke]

rickman wrote:

Xilinx likes to
pad the number since they feel they have "uber-cells" which count as
more than 1 each. But then again, they don't define the term "logic
cell", so I guess they can count them any way they want.

Not really, the "padding" is exactly 12.5%, so it has been defined and
is deterministic.
Marketing wants to get credit for the additional multiplexers that the
competition does not have.
If you are a purist, just count slices and devide by 2, or multiply CLBs
by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you
the number of LUTs+flip-flops.

Peter Alfke
>

 

[Peter Alfke]

Well, newness has its price.
But a year from now, the XC3S50 will be the low-cost champion,
especially in high volume...
But there is nothing wrong with using Spartan2, except for the smaller
BRAM and the simpler clock manager, compared to the upcoming production Spartan3-50....
Peter Alfke
===========================
Larry Doolittle wrote:

The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1.
The cheapest theoretical price I have seen for the XC3S50J is $23.85
(for a -4TQ144CES), and I have yet to see a distributor claim stock.

I know which one I would choose.

- Larry

 

[Larry Doolittle]

In article <3F688290.86C3AAC4@xilinx.com>, Peter Alfke wrote:

So you are looking for the XC2S30 (the next-to-smallest member) with the
equivalent of 864 LEs ( or the 2S50 with 1536 LE equivalents).
Your best bet for low price is the Spartan3 XC3S50 with 1536 LE
equivalents. This chip is available in an early version without BlockRAM.

The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1.
The cheapest theoretical price I have seen for the XC3S50J is $23.85
(for a -4TQ144CES), and I have yet to see a distributor claim stock.

I know which one I would choose.

- Larry

 

[Ray Andraka]

True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or
flip-flops instead.

Peter Alfke wrote:

rickman wrote:
Xilinx likes to
pad the number since they feel they have "uber-cells" which count as
more than 1 each. But then again, they don't define the term "logic
cell", so I guess they can count them any way they want.

Not really, the "padding" is exactly 12.5%, so it has been defined and
is deterministic.
Marketing wants to get credit for the additional multiplexers that the
competition does not have.
If you are a purist, just count slices and devide by 2, or multiply CLBs
by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you
the number of LUTs+flip-flops.

Peter Alfke

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Peter Alfke]

So, the 12.5% stand for "virtually useless" multiplexers, useful RAM
capability, and the super-useful SRL16 shift-register capability that
enhances Ray's formidable talents even more.

Peter Alfke
==================================
Ray Andraka wrote:

True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or
flip-flops instead.

P

 

[rickman]

Ray Andraka wrote:

True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic. Count 4-LUTs or
flip-flops instead.

Peter Alfke wrote:

rickman wrote:
Xilinx likes to
pad the number since they feel they have "uber-cells" which count as
more than 1 each. But then again, they don't define the term "logic
cell", so I guess they can count them any way they want.

Not really, the "padding" is exactly 12.5%, so it has been defined and
is deterministic.
Marketing wants to get credit for the additional multiplexers that the
competition does not have.
If you are a purist, just count slices and devide by 2, or multiply CLBs
by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you
the number of LUTs+flip-flops.

Peter Alfke

Personally, I find marketing to frequently be irritating and annoying.
When I try to get technical information from a data sheet or web site
and marketing distorts or glamorizes the information so much that it
interferes with my work, I find that both an insult to my intelligence
and a waste of my time.

I am aware of why Xilinx marketing distorts the cell counts and I don't
really care by how much. I care about the fact that I have to ignore a
column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Peter Alfke]

Rick, I will not defend the +12,5%, but I can explain it:

It is the price we all pay for the intense and sometimes ruthless
competition in this market. Without a bloodthirsty competitor "in our
rear-view mirror", we would be gentlemanlike and give you conservative
numbers. But the way it is, our marketing folks think it would throw
away some really (really!) powerful features if they are not somehow
represented in the numbers. Each Xilinx Logic Cell does more than an
Altera LE, there can be no doubt about that.

This is not an excuse (personally I agree with you), but an explanation.

Peter Alfke
==========================

rickman wrote:
I care about the fact that I have to ignore a

column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.

 

[Paul Leventis]

I might as well give the Altera view -- 12.5% is a gross overstatement of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
that nearly the reverse is true (about a 9% advantage for Stratix). Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you could
see vast density advantages from one architecture or the other.

http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf

If we wanted to, we could start counting our M512 blocks as logic, as they
can be used for shift-registers, small memories, and soft multipliers, but
we don't bother.

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Regards,

Paul Leventis
Altera Corp.



"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...

Rick, I will not defend the +12,5%, but I can explain it:

It is the price we all pay for the intense and sometimes ruthless
competition in this market. Without a bloodthirsty competitor "in our
rear-view mirror", we would be gentlemanlike and give you conservative
numbers. But the way it is, our marketing folks think it would throw
away some really (really!) powerful features if they are not somehow
represented in the numbers. Each Xilinx Logic Cell does more than an
Altera LE, there can be no doubt about that.

This is not an excuse (personally I agree with you), but an explanation.

Peter Alfke
==========================

rickman wrote:
I care about the fact that I have to ignore a
column of data in a data sheet as marketing hype and use a calculator to
get the *real* numbers. Clearly the marketing people don't think we can
add and multiply ourselves.

 

[Hal Murray]

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Is just recompiling good enough to be interesting? (Yes, better
than nothing and I'll take whatever I can get.)

Suppose I start with some "clean" vendor neutral code. How much do
I gain in speed or space by hacking the code to take advantage of
special features of an architecture?

If I have code that has been tweaked for one vendor, does that get
in the way (as compared to not help) if I just compile it for
another architecture?

How often is real code thoroughly tied to a particular chip?
Say by adjusting the pipeline to fit well. Or using a multiplier
as a shifter because it would otherwise be idle.
Or do all interesting FPGAs these days have multipliers and
dual port RAMs and ... that are reasonably equivalent?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Peter Alfke]

If anybody designs "vendor neutral" and relies on the compiler to get
the best implementation in, say, Xilinx and Altera, the result will most
likely the worst of all worlds.
FPGA architecture evolution is still young. Certain aspects are almost
standardized (4LUTs, carry, dual-ported RAMs, flexible-level I/O), but
each vendor tries to outdo the other with clever and (hopefully) useful
additions that the competitor does not (yet) have. Xilinx is very proud
of its LUTRAMs, SRL16s and DCMs with fine phase stepping. I assume that
Altera has their own very different goodies. There is no way that the
"generic compiler" will make good use of all this.
So it still takes a smart and imaginative designer to navigate between
all these exciting capabilities that differentiate the vendors. FPGA
are not (yet) a standardized commodity, the way automobiles have become
after 100 years of evolution. Thank God !
Peter Alfke

Hal Murray wrote:

Bottom line -- you really need to compile *your* design to both Stratix and
Virtex (or whatever families you are interested in) before you will really
know what the story is density. Averages don't matter much to you if yours
is that design that gets hosed in one architecture or the other!

Is just recompiling good enough to be interesting? (Yes, better
than nothing and I'll take whatever I can get.)

Suppose I start with some "clean" vendor neutral code. How much do
I gain in speed or space by hacking the code to take advantage of
special features of an architecture?

If I have code that has been tweaked for one vendor, does that get
in the way (as compared to not help) if I just compile it for
another architecture?

How often is real code thoroughly tied to a particular chip?
Say by adjusting the pipeline to fit well. Or using a multiplier
as a shifter because it would otherwise be idle.
Or do all interesting FPGAs these days have multipliers and
dual port RAMs and ... that are reasonably equivalent?

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Mike Treseler]

Hal Murray wrote:

Is just recompiling good enough to be interesting? (Yes, better
than nothing and I'll take whatever I can get.)

I always test synth code on both brands.

Suppose I start with some "clean" vendor neutral code. How much do
I gain in speed or space by hacking the code to take advantage of
special features of an architecture?

You can make significant improvements in speed and space.
The downside is a longer design time, a commitment
to a single family from a single vendor and
complications to simulation and design reuse.

If I have code that has been tweaked for one vendor, does that get
in the way (as compared to not help) if I just compile it for
another architecture?

In that case, you must learn the alternate architecture
and recode all of the vendor specific instances and attributes.

How often is real code thoroughly tied to a particular chip?

It's quite easy to do. Both brands A and X lead you down
that path with wizards, core generators and app notes.

Say by adjusting the pipeline to fit well. Or using a multiplier
as a shifter because it would otherwise be idle.

That is a design decision.
If you design with inference only, you lose some options.

Or do all interesting FPGAs these days have multipliers and
dual port RAMs and ... that are reasonably equivalent?

The common inferrable set includes carry chains, ram, rom and
and pseudo-dual port ram like this:


if rising_edge(clk) then
if we = '1' then
mem(to_integer(push_tail_ptr)) <= data_i; -- raw address
end if;
data_q <= mem(to_integer(pop_head_ptr)); -- mem data after pop low
end if;


-- Mike Treseler

 

[Ray Andraka]

So much so, that they stripped out half of the SRL16's and LUTRAMs in the
SpartanIII. In all fairness, that was because customers aren't using them to the
full advantage. The not using them is partially an education problem (Xilinx has
not done all that much to tout the SRL16), partly a synth tools problem (they don't
infer them except in the most obvious brain dead cases), and partly due to a
generic code mindset propagated by the EDA community.

Peter Alfke wrote:

... Xilinx is very proud of its LUTRAMs, SRL16s and DCMs with fine phase
stepping. ...

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Neil Franklin]

Peter Alfke <peter@xilinx.com> writes:

Ray Andraka wrote:

True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic.

No problem at all. 2 LUTs with F5 enabled may by double the vertical
size of an data path bit. But as one is not using the carry chain
when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem
to "zigzag" data path bits. Put each pair of data path bits into 2
vertical stripes of slices, very simple:

. . . .
. . . .
3 2 3 3 0..3.. = where bit gets processed
2 2>3> 2 > = enabled F5 MUX
1 0 1 1
0 0>1> 0

And with F5 being "vertical" it can be used (combining 2 LUTS to an 8
input AND or OR) in the corresponding control logic of an 1 slice wide
data path segment, without having to sacrifice an 2nd slice or use up
logic of the next (or even worse previous) segments control logic space.

Now F6 using 2 horizontally neighboring slices (which is what you
suggest for F5), that messes this scheme up.

So, the 12.5% stand for "virtually useless" multiplexers, useful RAM
capability, and the super-useful SRL16 shift-register capability that
enhances Ray's formidable talents even more.

Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in
multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive
F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless
SRL16s.

Everyone sees their 1/8th of an LUT in different extra features.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
code generates the software, have you coded today?

 

[rickman]

To Peter, Paul and all the other apostles...

My point is that as an engineer, I can figure out what is best for my
design. If I can't, then shame on me. But giving me phoney numbers
(which is what the Xilinx cell counts are no matter how marketing
justifies them) just makes the vendor look bad to engineers. If Xilinx
has better cells, then tell me that! Don't try to tell me you have more
cells than you really do, that is utter nonsense!!!

I have always and expect *will* always resent the "spin" that marketing
puts on what is really a very technical business. I remember the first
time I noticed an overly "marketized" web site that was hard to view
because of the large graphic files that added nothing to the information
I wanted. I also remember the first time an information file was
altered by marketing so much that it was not usable on any of the
machines I had available. I have yet to see any added value in any of
the documentation or even in the advertising that the marketing people
put out. Heck, it was only a few weeks ago that I even learned what a
"platform" chip was after having read about it in FPGA advertising for
what... three or four years?

Before we let Shakespeare kill all the lawyers, let's kill all the
marketeers!


Paul Leventis wrote:

I might as well give the Altera view -- 12.5% is a gross overstatement of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
that nearly the reverse is true (about a 9% advantage for Stratix). Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you could
see vast density advantages from one architecture or the other.

....snip...

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...
Rick, I will not defend the +12,5%, but I can explain it:

....snip...

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Simon Peacock]

I just noticed that HDD manufacturers are getting sued over binary Megabyte
vs. decimal megabyte.. perhaps they could do Xilinx when they are finished
??



But seriously..I hope Xilinx are watching.. I think the same rules would
have to apply here. chickens are chickens just don't count them until they
hatch

Simon

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F6E9C13.3B65F43E@yahoo.com...

To Peter, Paul and all the other apostles...

My point is that as an engineer, I can figure out what is best for my
design. If I can't, then shame on me. But giving me phoney numbers
(which is what the Xilinx cell counts are no matter how marketing
justifies them) just makes the vendor look bad to engineers. If Xilinx
has better cells, then tell me that! Don't try to tell me you have more
cells than you really do, that is utter nonsense!!!

I have always and expect *will* always resent the "spin" that marketing
puts on what is really a very technical business. I remember the first
time I noticed an overly "marketized" web site that was hard to view
because of the large graphic files that added nothing to the information
I wanted. I also remember the first time an information file was
altered by marketing so much that it was not usable on any of the
machines I had available. I have yet to see any added value in any of
the documentation or even in the advertising that the marketing people
put out. Heck, it was only a few weeks ago that I even learned what a
"platform" chip was after having read about it in FPGA advertising for
what... three or four years?

Before we let Shakespeare kill all the lawyers, let's kill all the
marketeers!


Paul Leventis wrote:

I might as well give the Altera view -- 12.5% is a gross overstatement
of
the relative abilities of a Virtex LC vs. a Stratix LE. Our data
suggests
that nearly the reverse is true (about a 9% advantage for Stratix).
Please
see the following whitepaper for our reasoning and data. As you can see
from Figure 1, your mileage will vary -- depending on your design, you
could
see vast density advantages from one architecture or the other.

...snip...

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F69D605.63B715DB@xilinx.com...
Rick, I will not defend the +12,5%, but I can explain it:

...snip...

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Lorenzo Lutti]

"rickman" <spamgoeshere4@yahoo.com> ha scritto nel messaggio
news:3F6E9C13.3B65F43E@yahoo.com...

just makes the vendor look bad to
engineers. [...]

Vendors look always bad to engineers. They shave, wear the tie in the
summer and look happy, and this makes look us ugly.

--
Lorenzo

 

[Ray Andraka]

Yes, in theory that is correct. I've had problems with the mapper and/or
floorplanner accepting F5 muxes packed this way in the past. Usually however, I
don't use them. Still, in most cases the Virtex2 architecture is a clean hands
down winner.

Neil Franklin wrote:

Peter Alfke <peter@xilinx.com> writes:
Ray Andraka wrote:

True, but those muxes are virtually useless for data path because the bit
pitch doesn't match the bit pitch of the arithmetic.

No problem at all. 2 LUTs with F5 enabled may by double the vertical
size of an data path bit. But as one is not using the carry chain
when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem
to "zigzag" data path bits. Put each pair of data path bits into 2
vertical stripes of slices, very simple:

. . . .
. . . .
3 2 3 3 0..3.. = where bit gets processed
2 2>3> 2 > = enabled F5 MUX
1 0 1 1
0 0>1> 0

And with F5 being "vertical" it can be used (combining 2 LUTS to an 8
input AND or OR) in the corresponding control logic of an 1 slice wide
data path segment, without having to sacrifice an 2nd slice or use up
logic of the next (or even worse previous) segments control logic space.

Now F6 using 2 horizontally neighboring slices (which is what you
suggest for F5), that messes this scheme up.

So, the 12.5% stand for "virtually useless" multiplexers, useful RAM
capability, and the super-useful SRL16 shift-register capability that
enhances Ray's formidable talents even more.

Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in
multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive
F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless
SRL16s.

Everyone sees their 1/8th of an LUT in different extra features.

--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith
- hardware runs the world, software controls the hardware
code generates the software, have you coded today?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759