Xilinx VHDL coding styles,lookin for a tutorial

[blisca]

Hi
I am lookin for information about good coding style when using Xilinx
devices(Spartan 3 mostly),i mean templates for correct and efficient
implementation of clock dividers,multiplexers,RAM and so on,so that the
result could be easy to analyze and syntethize to the tool

Many thanks

Diego

 

[Mike Treseler]

blisca wrote:

I am lookin for information about good coding style

I use the same clocked process template for
all of my synthesis code, for all designs
and for all devices. Examples here:

http://mysite.verizon.net/miketreseler/

-- Mike Treseler

 

[Tricky]

On 2 Dec, 17:33, "blisca" <bliscachiocciolinatiscalipuntoit> wrote:

Hi
I am lookin for information about good coding style when using Xilinx
devices(Spartan 3 mostly),i mean templates for correct and efficient
implementation of clock dividers,multiplexers,RAM and so on,so that the
result could be easy to analyze and syntethize to the tool

Many thanks

Diego

For Ram, Muxes, registers (ie. basic fabric) its normally just best to
write clear generic code that could be read by any synthesisor,
they're pretty good at interpreting what you mean for the given
device. Just remember to simulate, simulate, simulate before you
actually try and put it on a chip. There isnt really any specific
Xilinx template for code, other than directly instatiating the library
primitives.

As for clock dividers, you'd best stick with the DCM entity and read
up in the data sheet as to how it works. Afaik, its not so feasible to
infer a digital clock divider in RTL VHDL.

 

[LittleAlex]

On Dec 2, 10:33 am, "blisca" <bliscachiocciolinatiscalipuntoit> wrote:

Hi
I am looking for information about good coding style when using Xilinx
devices(Spartan 3 mostly),i mean templates for correct and efficient
implementation of clock dividers,multiplexers,RAM and so on,so that the
result could be easy to analyze and synthesize to the tool

Many thanks

Diego

When working with Spartan3 parts, I've found <www.xilinx.com> to be a
good resource.

<http://www.xilinx.com/support/documentation/application_notes/
xapp215.pdf> - "Design Tips for HDL ...
<http://www.xilinx.com/support/documentation/white_papers/wp275.pdf> -
"Make your Design Up to 50% Smaller ...
<http://www.xilinx.com/itp/xilinx10/books/docs/sim/sim.pdf> -
"Synthesis and Simulation Design Guide"
--- take a look at section 3 - "General Recommendations for Coding
Practices"

AL

 

[Tricky]

http://www.xilinx.com/support/documentation/application_notes/
xapp215.pdf> - "Design Tips for HDL ...

Hmm. This doc seems to have been revised in 2000 and they STILL
recommend using std_logic_arith/signed/unsigned.

Poor show Xilinx.

 

[Andy]

The Synthesis and Simulation design guide also still uses (clock'event
and clock = '1') instead of rising_edge(clock).

They recommend not using array ports anywhere.

They do not say anything about records, loops, variables or integers
(let alone numeric_std types).

For most users HDL coding starts out as "coding a shchematic netlist",
where specific processes or entities represent low level primitives
and constructs, interconnected together (the signals represent the
wires from the schematic).

But at some point, in order to improve design productivity above that
of drawing schematics or coding netlists, we have to raise the level
of abstraction. This includes not only effective use of data types,
but also the way we describe complex circuits. Abstraction also allows
us to focus on the intended behavior of the circuit, rather than its
structure. To be fair, when performance is pushing the limits of the
target device, a more structural-relative approach may be needed. But
in most cases, for most of a design, this is not necessary, and an
approach that more clearly relates the intended behavior is easier to
debug. When coupled with advanced optimizations such as register
replication and/or retiming, a behavioral approach is often just as
relevant to the structure of the implementation as a structural coding
approach would have been.

Like Mike Treseler, I use processes with variables to define the
behavior of a circuit. Signals are only used to connect between
processes in the same architecture, and often there is only one
(somewhat large) process per architecture, so there are no signals at
all. Descriptions and processes written this way "behave the way the
code reads", rather than having suspended updates of signal values,
etc. I do not use subprograms (functions or procedures) as a template
per se, but to collect and/or generalize reusable code.

Andy

 

[blisca]

Thanks to everybody here,you gave me lot of useful hints and lot of pages to
read.

I guess that you had got it yet

http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf

but i found this interesting link,and i post it in case you missed it

thanks again

Diego
Milan,Italy