Xilinx S3 I/O robustness question

Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models. Are you looking
into it? Is the part just to new and there is no information
available at your level?
 
lecroy wrote:
Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models. Are you looking
into it? Is the part just to new and there is no information
available at your level?
No one has responded to my posting here. This is not the sort of
question you can expect a good answer from by the hotline. So unless my
local rep can give me some straight talk, I will assume that the IBIS
models are still very preliminary and not of any real value for
simulation yet. BTW, I am having breakfast with my rep and sales person
today. We'll see what they have to say about the IBIS models and the
partial reconfiguration issues.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,

The IBIS models are based on the foundry spice models, which are pretty
mature now, as the same transistors used for the IOs have been manufactured
now for almost a year.

Just because others have absolutely lousy IBIS models out there does not
mean we do: We continually check the quality of the models. Yes, Spartan 3
has preliminary models but only because it is not released to production yet
-- it is still int he ES phase. This allows us to make changes easily as we
discover issues. So far, no issues with IBIS.

Austin

rickman wrote:

lecroy wrote:

Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models. Are you looking
into it? Is the part just to new and there is no information
available at your level?

No one has responded to my posting here. This is not the sort of
question you can expect a good answer from by the hotline. So unless my
local rep can give me some straight talk, I will assume that the IBIS
models are still very preliminary and not of any real value for
simulation yet. BTW, I am having breakfast with my rep and sales person
today. We'll see what they have to say about the IBIS models and the
partial reconfiguration issues.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Thanks for the answer.

Austin Lesea wrote:
Rick,

The IBIS models are based on the foundry spice models, which are pretty
mature now, as the same transistors used for the IOs have been manufactured
now for almost a year.

Just because others have absolutely lousy IBIS models out there does not
mean we do: We continually check the quality of the models. Yes, Spartan 3
has preliminary models but only because it is not released to production yet
-- it is still int he ES phase. This allows us to make changes easily as we
discover issues. So far, no issues with IBIS.

Austin

rickman wrote:

lecroy wrote:

Surely as hard as you Xilinx guys pushed simulation as the answer for
this, you would know the details of the S3 models. Are you looking
into it? Is the part just to new and there is no information
available at your level?

No one has responded to my posting here. This is not the sort of
question you can expect a good answer from by the hotline. So unless my
local rep can give me some straight talk, I will assume that the IBIS
models are still very preliminary and not of any real value for
simulation yet. BTW, I am having breakfast with my rep and sales person
today. We'll see what they have to say about the IBIS models and the
partial reconfiguration issues.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,

The IBIS models are based on the foundry spice models, which are pretty
mature now, as the same transistors used for the IOs have been manufactured
now for almost a year.

Just because others have absolutely lousy IBIS models out there does not
mean we do: We continually check the quality of the models. Yes, Spartan 3
has preliminary models but only because it is not released to production yet
-- it is still int he ES phase. This allows us to make changes easily as we
discover issues. So far, no issues with IBIS.

Austin
From a Xilinx S2 IBIS model..
Note " .... this model is considered preliminary as it has not been
verified by actual silicon measurement."
And this is an old part. How good do you think Xilinx models are for
the S3??


[Disclaimer] The data in this model is derived from SPICE
simulations using
modeling information extracted from the target
process. While
a great deal of care has been taken to provide
information
that is accurate, this model is considered
preliminary as it
has not been verified by actual silicon measurement.
Treat the
data in this model as preliminary until actual
silicon
verification is performed.
[Copyright] Copyright 2000, Xilinx Inc., All rights reserved
 
Standard disclaimer.

We don't seem to get around to removing the caveats.....I'll look into that.

All parts once they are in production have been verified in MY lab.

By the way, folks have asked about duty cycle distortion in the outputs, and IBIS
models will allow you to simulate the FAST/STRONG corner and then the SLOW/WEAK
corner. You can imagine that the rise vs. fall times could be (absolute worst
case) that different. Godd thing to check when you want to know "is this standard
fast enough for my xxxx application?"*

Austin

This does use the low vcc, low temp, high vcc, high temp as part of the corners
(as well as the process variation which is what you are really concerned about
here), so it is more pessimistic than the reality (reality can not have a low vcc,
hot rising edge with a high vcc cold falling edge), but it is still a great way to
check if the IO standard you have chosen is reasonably well matched for the speed
you desire.

lecroy wrote:

Rick,

The IBIS models are based on the foundry spice models, which are pretty
mature now, as the same transistors used for the IOs have been manufactured
now for almost a year.

Just because others have absolutely lousy IBIS models out there does not
mean we do: We continually check the quality of the models. Yes, Spartan 3
has preliminary models but only because it is not released to production yet
-- it is still int he ES phase. This allows us to make changes easily as we
discover issues. So far, no issues with IBIS.

Austin

From a Xilinx S2 IBIS model..
Note " .... this model is considered preliminary as it has not been
verified by actual silicon measurement."
And this is an old part. How good do you think Xilinx models are for
the S3??

[Disclaimer] The data in this model is derived from SPICE
simulations using
modeling information extracted from the target
process. While
a great deal of care has been taken to provide
information
that is accurate, this model is considered
preliminary as it
has not been verified by actual silicon measurement.
Treat the
data in this model as preliminary until actual
silicon
verification is performed.
[Copyright] Copyright 2000, Xilinx Inc., All rights reserved
 

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