Xilinx CPLD XC95144 for Driving Sigma Delta DAC

Tim Wescott <tim@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it
is -10C(means 10nsec delay for IO routs), does this delay impose
any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input,
and
by


You've written behavioral VHDL that describes a dual-port block RAM.
That's lovely and all, but have you checked the CPLD datasheet and
confirmed that there is a block RAM resource on the chip that will do
that? You could also write VHDL describing a unicorn, but you'd be
hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email
address domain is currently out of order. See above to fix.


I am some how obliged to use XC95144(since I have plenty of them
purchased before), and as it was mentioned here, I omitted RAM Module
from my design and instead I would like to add a SRAM or SDRAM chip,(and
since SDRAM is much cheaper than SRAM I'm apt to SDRAM), and here it
posed another question and that is if this CPLD is capable of driving a
SDRAM (regarding dynamic memory timing constraints)?

I'd go for SRAM. I have used the XC95144 for replacing CRT / STN
displays with TFT. The key is to calculate the required bandwidth. In my
most recent project I used a 16 bit SRAM.

Still, given your project requirements you probably could get by with a
small FIFO (maybe 4 bytes deep). You need to get enough data from the
microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.
Click to expand...
I guess ST is still making mediocre controllers. After an adventure
with the STR700 series I switched to NXP and never looked back at ST.
Appearantly a good choice :)

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:

Tim Wescott <tim@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C),
it is -10C(means 10nsec delay for IO routs), does this delay
impose any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input,
and
by


You've written behavioral VHDL that describes a dual-port block RAM.
That's lovely and all, but have you checked the CPLD datasheet and
confirmed that there is a block RAM resource on the chip that will do
that? You could also write VHDL describing a unicorn, but you'd be
hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email
address domain is currently out of order. See above to fix.


I am some how obliged to use XC95144(since I have plenty of them
purchased before), and as it was mentioned here, I omitted RAM Module
from my design and instead I would like to add a SRAM or SDRAM
chip,(and since SDRAM is much cheaper than SRAM I'm apt to SDRAM), and
here it posed another question and that is if this CPLD is capable of
driving a SDRAM (regarding dynamic memory timing constraints)?

I'd go for SRAM. I have used the XC95144 for replacing CRT / STN
displays with TFT. The key is to calculate the required bandwidth. In
my most recent project I used a 16 bit SRAM.

Still, given your project requirements you probably could get by with
a small FIFO (maybe 4 bytes deep). You need to get enough data from
the microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.

I guess ST is still making mediocre controllers. After an adventure with
the STR700 series I switched to NXP and never looked back at ST.
Appearantly a good choice :)
Click to expand...
35MHz clock at the peripheral -- the ST chip he's looking at is rated for
70 or 72MHz or some such.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
 
Tim Wescott <tim@seemywebsite.com> wrote:

On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:

Tim Wescott <tim@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the

Still, given your project requirements you probably could get by with
a small FIFO (maybe 4 bytes deep). You need to get enough data from
the microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.

I guess ST is still making mediocre controllers. After an adventure with
the STR700 series I switched to NXP and never looked back at ST.
Appearantly a good choice :)

35MHz clock at the peripheral -- the ST chip he's looking at is rated for
70 or 72MHz or some such.
Click to expand...
AFAIK most ST devices can't run from flash at their rated clock
speeds. NXP's can and some go up to 120MHz (180MHz is on its way)!

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
On Sep 28, 2:54 am, n...@puntnl.niks (Nico Coesel) wrote:
Tim Wescott <t...@seemywebsite.com> wrote:
On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:

Tim Wescott <t...@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the

Still, given your project requirements you probably could get by with
a small FIFO (maybe 4 bytes deep). You need to get enough data from
the microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.

I guess ST is still making mediocre controllers. After an adventure with
the STR700 series I switched to NXP and never looked back at ST.
Appearantly a good choice :)

35MHz clock at the peripheral -- the ST chip he's looking at is rated for
70 or 72MHz or some such.

AFAIK most ST devices can't run from flash at their rated clock
speeds. NXP's can and some go up to 120MHz (180MHz is on its way)!
Click to expand...
STM32F4 has a flash accelerator similar to NXP and run at full speed
168MHz

the stm32f107 looks to have 2x I2S that can run at pclk/2 the ad1933
can run
dual line so I think it should be possible

-Lasse
 
On Fri, 28 Sep 2012 00:54:34 +0000, Nico Coesel wrote:

Tim Wescott <tim@seemywebsite.com> wrote:

On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:

Tim Wescott <tim@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500 "nba83" <3224@embeddedrelated
wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how
concerned
about
the

Still, given your project requirements you probably could get by
with a small FIFO (maybe 4 bytes deep). You need to get enough data
from the microcontroller. OTOH it sounds like a lot of fuss to keep
the microcontroller. If you switch to an ARM device (NXP for
instance) you can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.

I guess ST is still making mediocre controllers. After an adventure
with the STR700 series I switched to NXP and never looked back at ST.
Appearantly a good choice :)

35MHz clock at the peripheral -- the ST chip he's looking at is rated
for 70 or 72MHz or some such.

AFAIK most ST devices can't run from flash at their rated clock speeds.
NXP's can and some go up to 120MHz (180MHz is on its way)!
Click to expand...
Yes, good point. And part of my point to the OP is that once he solves
his ADC throughput problem, is he going to be able to generate the data?

Depending on his application, a teeny bit of code running out of RAM in
the '107 may be enough. Or, the app may self-destruct on a ton of code
running at 120MHz on your NXP.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
 
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