Xilinx CPLD XC95144 for Driving Sigma Delta DAC

[nba83]

hi
i would like to drive a Digital to analog converter(AD1933) with a cpld
here is what i'm trying to do: i have a micro controller that generat
25Mbps DAC data but is not capable of driving the DAC through high spee
SPI(i need over 35MHz spi interface), so i decided to drive the dac wit
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer t
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld i
capable of driving the dac at this rate, any one have any idea about th
feasibility of this plan??
tnx in advance for help


---------------------------------------
Posted through http://www.FPGARelated.com

 

[Tim Wescott]

On Sun, 23 Sep 2012 00:57:27 -0500, nba83 wrote:

hi i would like to drive a Digital to analog converter(AD1933) with a
cpld, here is what i'm trying to do: i have a micro controller that
generate 25Mbps DAC data but is not capable of driving the DAC through
high speed SPI(i need over 35MHz spi interface), so i decided to drive
the dac with cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld
is capable of driving the dac at this rate, any one have any idea about
the feasibility of this plan??
tnx in advance for help

How are you going to get data into your CPLD at that rate? Parallel?
Some other serial interface that also needs to run at 35MHz or more?

Your feasibility may break up on other rocks than whether the CPLD is up
to it.

Having said that -- to my beginner's eyes a parallel in, serial out,
35MHz SPI should be doable with a part like that.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

 

[rickman]

On 9/23/2012 1:57 AM, nba83 wrote:

hi
i would like to drive a Digital to analog converter(AD1933) with a cpld,
here is what i'm trying to do: i have a micro controller that generate
25Mbps DAC data but is not capable of driving the DAC through high speed
SPI(i need over 35MHz spi interface), so i decided to drive the dac with
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld is
capable of driving the dac at this rate, any one have any idea about the
feasibility of this plan??
tnx in advance for help

Without looking at the data sheet, I am pretty sure these parts can
drive a 35 MHz serial shift register. 35 MHz is pretty slow for any
programmable logic part.

How will the CPLD talk to the micro? I assume you plan to use a
parallel, memory mapped interface? Can your MCU keep up with the data
speed?

Rick

 

[rickman]

On 9/23/2012 4:27 PM, rickman wrote:

On 9/23/2012 1:57 AM, nba83 wrote:
hi
i would like to drive a Digital to analog converter(AD1933) with a cpld,
here is what i'm trying to do: i have a micro controller that generate
25Mbps DAC data but is not capable of driving the DAC through high speed
SPI(i need over 35MHz spi interface), so i decided to drive the dac with
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this
cpld is
capable of driving the dac at this rate, any one have any idea about the
feasibility of this plan??
tnx in advance for help

Without looking at the data sheet, I am pretty sure these parts can
drive a 35 MHz serial shift register. 35 MHz is pretty slow for any
programmable logic part.

How will the CPLD talk to the micro? I assume you plan to use a
parallel, memory mapped interface? Can your MCU keep up with the data
speed?

Rick

BTW, there are some very low cost FPGAs available, around $3. Check out
the Lattice ice40 series.

Rick

 

[Nico Coesel]

"nba83" <3224@embeddedrelated> wrote:

hi
i would like to drive a Digital to analog converter(AD1933) with a cpld,
here is what i'm trying to do: i have a micro controller that generate
25Mbps DAC data but is not capable of driving the DAC through high speed
SPI(i need over 35MHz spi interface), so i decided to drive the dac with
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld is
capable of driving the dac at this rate, any one have any idea about the
feasibility of this plan??

It shouldn't be a problem. I use these CPLDs for rescaling VGA
resolution TFT displays at reduced color depths.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[nba83]

How are you going to get data into your CPLD at that rate? Parallel?
Some other serial interface that also needs to run at 35MHz or more?

Your feasibility may break up on other rocks than whether the CPLD is up
to it.

Having said that -- to my beginner's eyes a parallel in, serial out,
35MHz SPI should be doable with a part like that.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

I want to feed data in parallel (8bit) to CPLD, buffer it for about 10
bytes, and then start to drive SPI Out. I am some how concerned about th
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it i
-10C(means 10nsec delay for IO routs), does this delay impose any problem
Since I want to drive the CPLD with 100MHZ oscillator clk input, and by cl
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments


---------------------------------------
Posted through http://www.FPGARelated.com

 

[Arlet Ottens]

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for about 100
bytes, and then start to drive SPI Out. I am some how concerned about the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is
-10C(means 10nsec delay for IO routs), does this delay impose any problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input, and by clk
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments

The problem isn't going to be the speed, but where the CPLD is going to
store the 100 bytes. The XC95144XL only has 144 bits of storage total.

 

[nba83]

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for about 100
bytes, and then start to drive SPI Out. I am some how concerned abou
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is
-10C(means 10nsec delay for IO routs), does this delay impose an
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input, and b
clk
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments

The problem isn't going to be the speed, but where the CPLD is going to
store the 100 bytes. The XC95144XL only has 144 bits of storage total.

I have implemented a 1k byte dual port ram in this cpld logic in xilin
ise, but i havn't tested it yet. I have not added the DAC driver to it yet
i'm not sure if this cpld is enough for these modules. here is th
implementation for RAM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dpram_4x2045 is
Port ( DIN : in std_logic_vector(7 downto 0);
RE_ADDRESS : in std_logic_vector(10 downto 0);
wr_address :in std_logic_vector(10 downto 0);
CLCK_wr : in std_logic;
CLCK_re : in std_logic;
We : in std_logic;
Re : in std_logic;
dout : out std_logic_vector(7 downto 0));
end dpram_4x2045 ;

architecture Behavioral of dpram_4x2045 is
type my_data is array (0 to 2048)of std_logic_vector(7 downto 0) ;
signal rom: my_data;
begin

process (clck_wr)--write
begin
if (clck_wr'event and clck_wr = '0') then
if (we = '1') then
rom(conv_integer(WR_address)) <= din;

end if;
end if;
end process;

process (clck_re)--read
begin
if (clck_re'event and clck_re = '1') then ---e
if (Re = '1') then
dout<=rom(conv_integer(RE_address));
end if;

end if;
end process;

end Behavioral;

and the other module will receive bytes from parallel port and write it i
buffer, after writing 100 bytes, spi out module is enabled. and send ou
data bytes

---------------------------------------
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[Rob Gaddi]

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for about 100
bytes, and then start to drive SPI Out. I am some how concerned about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is
-10C(means 10nsec delay for IO routs), does this delay impose any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input, and by
clk
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments

The problem isn't going to be the speed, but where the CPLD is going to
store the 100 bytes. The XC95144XL only has 144 bits of storage total.



I have implemented a 1k byte dual port ram in this cpld logic in xilinx
ise, but i havn't tested it yet. I have not added the DAC driver to it yet,
i'm not sure if this cpld is enough for these modules. here is the
implementation for RAM:

You've written behavioral VHDL that describes a dual-port
block RAM. That's lovely and all, but have you checked the CPLD
datasheet and confirmed that there is a block RAM resource on the chip
that will do that? You could also write VHDL describing a unicorn, but
you'd be hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[Jon Elson]

nba83 wrote:

hi
i would like to drive a Digital to analog converter(AD1933) with a cpld,
here is what i'm trying to do: i have a micro controller that generate
25Mbps DAC data but is not capable of driving the DAC through high speed
SPI(i need over 35MHz spi interface), so i decided to drive the dac with
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld
is capable of driving the dac at this rate, any one have any idea about
the feasibility of this plan??
The 9500XL series starts out very cheap, but the larger components,

like the 95144, start to get expensive. You can check the prices of
the CoolRunner series (XCR), also quite cheap even in the larger sizes.
But, you are talking about significant amounts of registers, and
the CPLDs are very short on them. Block RAMs don't exist at all
on Xilinx CPLDs, and probably not on anybody else's, either.

The smaller Spartan 3A are quite inexpensive, but need a download
serial PROM. SST's 25VF010A will load the XC3S50A FPGA with no
additional chips, and is under $1 in small quantity. You can get the
Spartan 3AN version of the FPGA with built-in SPROM, but it costs
more than the separate solution. You do need to find a way to
program the SST SPROM, but it is fairly easy to do. Totally minimal
hardware, and pretty simple software.

Jon

 

[nba83]

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for abou
100
bytes, and then start to drive SPI Out. I am some how concerne
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is
-10C(means 10nsec delay for IO routs), does this delay impose any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input, an
by
clk
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments

The problem isn't going to be the speed, but where the CPLD is going t

store the 100 bytes. The XC95144XL only has 144 bits of storage total.



I have implemented a 1k byte dual port ram in this cpld logic i
xilinx
ise, but i havn't tested it yet. I have not added the DAC driver to i
yet,
i'm not sure if this cpld is enough for these modules. here is the
implementation for RAM:


You've written behavioral VHDL that describes a dual-port
block RAM. That's lovely and all, but have you checked the CPLD
datasheet and confirmed that there is a block RAM resource on the chip
that will do that? You could also write VHDL describing a unicorn, but
you'd be hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

I am some how obliged to use XC95144(since I have plenty of them purchase
before), and as it was mentioned here, I omitted RAM Module from my desig
and instead I would like to add a SRAM or SDRAM chip,(and since SDRAM i
much cheaper than SRAM I'm apt to SDRAM), and here it posed anothe
question and that is if this CPLD is capable of driving a SDRAM (regardin
dynamic memory timing constraints)?
tnx in advance for any helpful comment
Neda Baheri

---------------------------------------
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[jg]

On Tuesday, September 25, 2012 11:09:14 PM UTC+12, nba83 wrote:

I would like to add a SRAM or SDRAM chip,(and since SDRAM is
much cheaper than SRAM I'm apt to SDRAM), and here it posed another

SDRAM is only cheaper than SRAM well above the 100 bytes you claimed to need.
For small storage, your RAM choices would be Parallel 256k bit (tends to be cheapest size), or you could look at the QuadSPI SRAM from Microchip.
That is SO8, and can do 80MBit (20MHz x 4)
-jg

 

[Tim Wescott]

On Tue, 25 Sep 2012 06:09:13 -0500, nba83 wrote:

On Mon, 24 Sep 2012 06:00:15 -0500 "nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it
is -10C(means 10nsec delay for IO routs), does this delay impose
any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input,
and
by
clk
dividing generate a 50 or 40MHz clk for SPI.
tnx for any helpful comments

The problem isn't going to be the speed, but where the CPLD is going
to

store the 100 bytes. The XC95144XL only has 144 bits of storage
total.



I have implemented a 1k byte dual port ram in this cpld logic in
xilinx
ise, but i havn't tested it yet. I have not added the DAC driver to it
yet,
i'm not sure if this cpld is enough for these modules. here is the
implementation for RAM:


You've written behavioral VHDL that describes a dual-port block RAM.
That's lovely and all, but have you checked the CPLD datasheet and
confirmed that there is a block RAM resource on the chip that will do
that? You could also write VHDL describing a unicorn, but you'd be hard
pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email
address domain is currently out of order. See above to fix.


I am some how obliged to use XC95144(since I have plenty of them
purchased before), and as it was mentioned here, I omitted RAM Module
from my design and instead I would like to add a SRAM or SDRAM chip,(and
since SDRAM is much cheaper than SRAM I'm apt to SDRAM), and here it
posed another question and that is if this CPLD is capable of driving a
SDRAM (regarding dynamic memory timing constraints)?
tnx in advance for any helpful comment Neda Baheri

It seems to me that you're rapidly approaching a point where your
cheapest solution is to cast your XC95144s in a block of clear epoxy to
hand out as a trophy, and switch to a microprocessor that's up to the
task.

Do you really need to implement a FIFO in the CPLD? Can't you just have
the microprocessor write out the transaction (in parallel) each time you
need it to come out the CPLD, thereby obviating the need or all the
memory?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

 

[nba83]

Do you really need to implement a FIFO in the CPLD? Can't you just have
the microprocessor write out the transaction (in parallel) each time you
need it to come out the CPLD, thereby obviating the need or all the
memory?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

the microprocessor is ARM Corex M3(Stm32f107) which has really slow IOs
writing 16 bits, setting and resetting a control pin takes about 1Usec,
need to transfer 8ch*16bit within 5 usec, so I need to buffer dat
somewhere outside microprocessor. I'm in the design phase of projec
prototype, and I want to consider any cheap available option in the board
in software development phase some of the chips may be omitted.

---------------------------------------
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[Stef]

In comp.arch.fpga,
nba83 <3224@embeddedrelated> wrote:

Do you really need to implement a FIFO in the CPLD? Can't you just have
the microprocessor write out the transaction (in parallel) each time you
need it to come out the CPLD, thereby obviating the need or all the
memory?


the microprocessor is ARM Corex M3(Stm32f107) which has really slow IOs,
writing 16 bits, setting and resetting a control pin takes about 1Usec, I
need to transfer 8ch*16bit within 5 usec, so I need to buffer data
somewhere outside microprocessor. I'm in the design phase of project
prototype, and I want to consider any cheap available option in the board,
in software development phase some of the chips may be omitted.

Are you bitbanging this? Seems the STM32F107 has an I2S interface and so
has the AD1933. Aren't the two working together, or is the another reason
you can not use the I2S peripheral?

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

I sometimes think that God, in creating man, somewhat overestimated his ability.
-- Oscar Wilde

 

[nba83]

Are you bitbanging this? Seems the STM32F107 has an I2S interface and so
has the AD1933. Aren't the two working together, or is the another reaso

you can not use the I2S peripheral?



Stm32 only supports rates 8 KHz to 96 KHz, I want to drive the chip at 19

KHz
which Stm does not provide

---------------------------------------
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[Tim Wescott]

On Wed, 26 Sep 2012 11:49:32 -0500, nba83 wrote:

Are you bitbanging this? Seems the STM32F107 has an I2S interface and so
has the AD1933. Aren't the two working together, or is the another
reason

you can not use the I2S peripheral?



Stm32 only supports rates 8 KHz to 96 KHz, I want to drive the chip at
192 KHz
which Stm does not provide

Things aren't lining up here.

192kHz sampling? Over 35MHz bit rate? That works out to over 182bits/
sample. How many bits per channel? How many channels?

That chip will run at something like a 72MHz core clock, which gives you
36MHz at the SPI. Moreover, if the ADC demands (say) 32 bits/write, then
you've got 64 clock cycles per word out if the chip is running flat out
-- that leads me to believe that if you can't pump this out the SPI port
of that chip, you're not going to be able to do anything significant to
the data while it's in the processor. Unless (and probably even if) you
hand-code the thing in assembly and run it out of RAM, you're not going
to be able to do much more than read the data out of memory and shove it
out the door.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

 

[langwadt@fonz.dk]

On Sep 26, 8:41 pm, Tim Wescott <t...@seemywebsite.com> wrote:

On Wed, 26 Sep 2012 11:49:32 -0500, nba83 wrote:
Are you bitbanging this? Seems the STM32F107 has an I2S interface and so
has the AD1933. Aren't the two working together, or is the another
reason

you can not use the I2S peripheral?

Stm32 only supports rates 8 KHz to 96 KHz, I want to drive the chip at
192 KHz
 which Stm does not provide

Things aren't lining up here.

192kHz sampling?  Over 35MHz bit rate?  That works out to over 182bits/
sample.  How many bits per channel?  How many channels?

first post mentioned ad1933, 8channels,24bit,192kHz so 36.864MHz

That chip will run at something like a 72MHz core clock, which gives you
36MHz at the SPI.  Moreover, if the ADC demands (say) 32 bits/write, then
you've got 64 clock cycles per word out if the chip is running flat out
-- that leads me to believe that if you can't pump this out the SPI port
of that chip, you're not going to be able to do anything significant to
the data while it's in the processor.  Unless (and probably even if) you
hand-code the thing in assembly and run it out of RAM, you're not going
to be able to do much more than read the data out of memory and shove it
out the door.

SPI is just for setup, data goes on I2S, running the mcu at 73.728MHz
and
using DMA it might work (assuming the I2S can run at mcuclk/2)

-Lasse

 

[Nico Coesel]

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is
-10C(means 10nsec delay for IO routs), does this delay impose any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input, and
by


You've written behavioral VHDL that describes a dual-port
block RAM. That's lovely and all, but have you checked the CPLD
datasheet and confirmed that there is a block RAM resource on the chip
that will do that? You could also write VHDL describing a unicorn, but
you'd be hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.


I am some how obliged to use XC95144(since I have plenty of them purchased
before), and as it was mentioned here, I omitted RAM Module from my design
and instead I would like to add a SRAM or SDRAM chip,(and since SDRAM is
much cheaper than SRAM I'm apt to SDRAM), and here it posed another
question and that is if this CPLD is capable of driving a SDRAM (regarding
dynamic memory timing constraints)?

I'd go for SRAM. I have used the XC95144 for replacing CRT / STN
displays with TFT. The key is to calculate the required bandwidth. In
my most recent project I used a 16 bit SRAM.

Still, given your project requirements you probably could get by with
a small FIFO (maybe 4 bytes deep). You need to get enough data from
the microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[Tim Wescott]

On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:

"nba83" <3224@embeddedrelated> wrote:

On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

On 09/24/2012 08:09 AM, nba83 wrote:

I want to feed data in parallel (8bit) to CPLD, buffer it for
about
100
bytes, and then start to drive SPI Out. I am some how concerned
about
the
speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it
is -10C(means 10nsec delay for IO routs), does this delay impose
any
problem?
Since I want to drive the CPLD with 100MHZ oscillator clk input,
and
by


You've written behavioral VHDL that describes a dual-port block RAM.
That's lovely and all, but have you checked the CPLD datasheet and
confirmed that there is a block RAM resource on the chip that will do
that? You could also write VHDL describing a unicorn, but you'd be
hard pressed to make it pass synthesis.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email
address domain is currently out of order. See above to fix.


I am some how obliged to use XC95144(since I have plenty of them
purchased before), and as it was mentioned here, I omitted RAM Module
from my design and instead I would like to add a SRAM or SDRAM chip,(and
since SDRAM is much cheaper than SRAM I'm apt to SDRAM), and here it
posed another question and that is if this CPLD is capable of driving a
SDRAM (regarding dynamic memory timing constraints)?

I'd go for SRAM. I have used the XC95144 for replacing CRT / STN
displays with TFT. The key is to calculate the required bandwidth. In my
most recent project I used a 16 bit SRAM.

Still, given your project requirements you probably could get by with a
small FIFO (maybe 4 bytes deep). You need to get enough data from the
microcontroller. OTOH it sounds like a lot of fuss to keep the
microcontroller. If you switch to an ARM device (NXP for instance) you
can reach >30MHz SPI easely and use DMA.

He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
need more than 35MHz.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com