Why VHDL?

[Anssi Saari]

gtwrek@sonic.net (Mark Curry) writes:

Anssi - Thanks very much for the links.

I think todays designers must be able to work with either VHDL or Verilog.
These language wars are over.

You're welcome and it's good share good information. I really meant to
continue that I've mostly worked in VHDL for the last few years. I guess
if I had to write Verilog now I'd be more than a little rusty.

straight-up code up a new entity? Errgh, I trip up everytime
on the basics. What Library to "use". What types to declare, etc.
For a Verilog user that runs loosey goosey around around typing and
bit vectors vs arithmetic context, etc, getting the right "Recipe"
for VHDL takes some relearning for me everytime.

Well, it's also a question of editors. Emacs may have a bit of a
learning curve but the VHDL mode for it is just awesome with templates
and completion. And the best part, it can paste an entity as an instance
or component declaration, so no more writing almost the same thing in
triplicate. I think I'd probably have trouble with VHDL as well if I
didn't have all that.

Sure it's pretty easy for you to remember - you probably
use it almost every day!

True

I wasn't aware of these guides, and I'm glad to now have them.

Jim's guide list the three main libs, "numeric_std", "std_logic_arith", and
"std_logic_unsigned". I belive however, that most modern styles suggest
JUST using "numeric_std" correct? (Jim's guide is from 2003).
(I remember more than one VHDL expert strongly suggesting not to use one
or the other, but I can't remember which was which...)

Yes, numeric_std. I have some old code to maintain and I don't want
change stuff around if I don't have to so I just leave the old stuff as
is (and it's good Jim covers the old stuff). But sometimes I have to
change something and then the binary literals and other hard to read
stuff just get the boot...