Why there is multi-source error?

[fl]

Hi,
The following code is for address decode at different states. I always
have the error message:


ERROR:Xst:528 - Multi-source in Unit <vhdl_qr0> on signal <RAM_in<1>>
Sources are:
Output signal of FDC instance <comp1/RAM_out_1>
Signal <RAM_in<1>> in Unit <vhdl_0> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <vhdl_0> on signal <RAM_in<0>>
Sources are:
Output signal of FDC instance <comp1/RAM_in_r0>
Signal <RAM_in<0>> in Unit <vhdl_0> is assigned to GND
CPU : 14.22 / 14.37 s | Elapsed : 14.00 / 14.00 s

-->

Total memory usage is 418028 kilobytes

Number of errors : 6 ( 0 filtered)
Number of warnings : 169 ( 0 filtered)
Number of infos : 4 ( 0 filtered)

----------------

I cannot understand the reason. In fact, the code is just like a VHDL
textbook's. What's wrong with it? Thanks.




state_p: process(state)
begin
case state is
when init =>
RAM_in <= "000";
RAM_out <= "001";
next_state <= st0;
when st0 =>
RAM_in_selection <= "010";
RAM_out_selection <= "011";
next_state <= st1;
when st1 =>
RAM_in_selection <= "100";
RAM_out_selection <= "101";
next_state <= init;
when others =>
RAM_in_selection <= "000";
RAM_out_selection <= "001";
next_state <= init;
end case;
end process;

 

[Tricky]

On Aug 24, 9:02 pm, fl <rxjw...@gmail.com> wrote:

Hi,
The following code is for address decode at different states. I always
have the error message:

ERROR:Xst:528 - Multi-source in Unit <vhdl_qr0> on signal <RAM_in<1
Sources are:
   Output signal of FDC instance <comp1/RAM_out_1
   Signal <RAM_in<1>> in Unit <vhdl_0> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <vhdl_0> on signal <RAM_in<0
Sources are:
   Output signal of FDC instance <comp1/RAM_in_r0
   Signal <RAM_in<0>> in Unit <vhdl_0> is assigned to GND
CPU : 14.22 / 14.37 s | Elapsed : 14.00 / 14.00 s

--

Total memory usage is 418028 kilobytes

Number of errors   :    6 (   0 filtered)
Number of warnings :  169 (   0 filtered)
Number of infos    :    4 (   0 filtered)

----------------

I cannot understand the reason. In fact, the code is just like a VHDL
textbook's. What's wrong with it? Thanks.

state_p: process(state)
begin
   case state is
     when init =
        RAM_in   <= "000";
        RAM_out <= "001";
        next_state <= st0;
    when st0 =
       RAM_in_selection  <= "010";
       RAM_out_selection <= "011";
       next_state <= st1;
   when st1 =
      RAM_in_selection  <= "100";
      RAM_out_selection <= "101";
      next_state <= init;
  when others =
      RAM_in_selection  <= "000";
      RAM_out_selection <= "001";
      next_state <= init;
  end case;
end process;

I dont think theres a problem with this level of VHD. it looks like
its the level above. The problem is that the signal RAM_in is being
driven from more than 1 source, from the looks of it the outputs from
1 block and you've assigned RAM_in <= "00" somewhere.

 

[h.e.]

state_p: process(state)
begin
case state is
when init =
RAM_in <= "000";
RAM_out <= "001";
next_state <= st0;
when st0 =
RAM_in_selection <= "010";
RAM_out_selection <= "011";
next_state <= st1;
when st1 =
RAM_in_selection <= "100";
RAM_out_selection <= "101";
next_state <= init;
when others =
RAM_in_selection <= "000";
RAM_out_selection <= "001";
next_state <= init;
end case;
end process;

Are you sure it is correct to assign RAM_in and RAM_out in the init
state, whereas all other states assign values to RAM_in_selection and
RAM_out_selection. As your code is written, it should create latches...
I assume you are assigning RAM_in and RAM_out in another part of your
design?