F
fl
Guest
Hi,
I am learning VHDL by exercises. I find a self defined type signal
cannot assign value more than one time, see below example please.
type symbol is ('a', 't', 'd', digit, cr, other);
signal ss : symbol;
BEGIN
ss <= 't';
ss <= 'a';
Modelsim gives the following error message:
** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41):
Nonresolved signal 'ss' has multiple sources.
It is different from the built-in types? Thanks you very much.
I am learning VHDL by exercises. I find a self defined type signal
cannot assign value more than one time, see below example please.
type symbol is ('a', 't', 'd', digit, cr, other);
signal ss : symbol;
BEGIN
ss <= 't';
ss <= 'a';
Modelsim gives the following error message:
** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41):
Nonresolved signal 'ss' has multiple sources.
It is different from the built-in types? Thanks you very much.