Why Doesn't VHDL Have a Wildcard Sensitivity List?

[rickman]

On Jan 23, 3:22 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:

rickman wrote:
On Jan 23, 12:23 pm, Mike Treseler <mtrese...@gmail.com> wrote:
I guess the downside of this is that it can get pretty messy to
describe a complex process as functions, which is pretty much what we
are talking about.
I disagree. A function is a clean way
to hide an asynchronous process and
the wires and sensitivity that go with it.

Whaaa..?  What wires does it hide that doesn't happen in a process?

A function that works on intermediate/temporary variables
within a clocked process can create combinatorial logic
without requiring sensitivity specifications.

Big news?

And how exactly is that different from a process??? Sounds to me like
no news at all.

Rick

 

[Jan Decaluwe]

rickman wrote:

On Jan 23, 3:22 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:
On Jan 23, 12:23 pm, Mike Treseler <mtrese...@gmail.com> wrote:
I guess the downside of this is that it can get pretty messy to
describe a complex process as functions, which is pretty much what we
are talking about.
I disagree. A function is a clean way
to hide an asynchronous process and
the wires and sensitivity that go with it.
Whaaa..? What wires does it hide that doesn't happen in a process?
A function that works on intermediate/temporary variables
within a clocked process can create combinatorial logic
without requiring sensitivity specifications.

Big news?

And how exactly is that different from a process???

Again, because functions don't have sensitivity lists of course!

Still, they are guaranteed to have combinatorial semantics as
they can't have side effects in VHDL.

Jan

--
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[backhus]

On 21 Jan., 22:28, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Thu, 20 Jan 2011 23:37:50 -0800 (PST), backhus wrote:
if you want to implement the all keyword in your favorite synthesis
tool, you can do it like this:

signal all : std_logic ;

Now you can use

process(all)

in your non-VHDL2008 synthesis tool, and it won't throw errors.

I fear not.  'all' is already a reserved word in every
version of the VHDL standard that I know of. (Think of
"use ieee.std_logic_1164.all;")

Cute idea, though.
--
Jonathan Bromley

Hi Jonathan,
*$%&! You're right, of course.
My only excuse is that the library stuff is handled by templates in
99.9% of my sources.

Sorry everybody for causing confusion.

Regards
Eilert

 

[rickman]

On Jan 24, 3:31 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:

rickman wrote:
On Jan 23, 3:22 pm, Jan Decaluwe <j...@jandecaluwe.com> wrote:
rickman wrote:
On Jan 23, 12:23 pm, Mike Treseler <mtrese...@gmail.com> wrote:
I guess the downside of this is that it can get pretty messy to
describe a complex process as functions, which is pretty much what we
are talking about.
I disagree. A function is a clean way
to hide an asynchronous process and
the wires and sensitivity that go with it.
Whaaa..?  What wires does it hide that doesn't happen in a process?
A function that works on intermediate/temporary variables
within a clocked process can create combinatorial logic
without requiring sensitivity specifications.

Big news?

And how exactly is that different from a process???  

Again, because functions don't have sensitivity lists of course!

Still, they are guaranteed to have combinatorial semantics as
they can't have side effects in VHDL.

So in regards to hiding the "wires", they are not different at all...

Rick

 

[Mike Treseler]

On 1/24/2011 6:47 AM, rickman wrote:

On Jan 24, 3:31 am, Jan Decaluwe<j...@jandecaluwe.com> wrote:
rickman wrote:
On Jan 23, 3:22 pm, Jan Decaluwe<j...@jandecaluwe.com> wrote:
rickman wrote:
On Jan 23, 12:23 pm, Mike Treseler<mtrese...@gmail.com> wrote:
I guess the downside of this is that it can get pretty messy to
describe a complex process as functions, which is pretty much what we
are talking about.
I disagree. A function is a clean way
to hide an asynchronous process and
the wires and sensitivity that go with it.
Whaaa..? What wires does it hide that doesn't happen in a process?
A function that works on intermediate/temporary variables
within a clocked process can create combinatorial logic
without requiring sensitivity specifications.

Big news?

And how exactly is that different from a process???

Again, because functions don't have sensitivity lists of course!

Still, they are guaranteed to have combinatorial semantics as
they can't have side effects in VHDL.

So in regards to hiding the "wires", they are not different at all...

This thread is about the vhdl process sensitivity list and how to avoid
simulation problems if I use it for anything other than the clock
or reset inputs. This question has been answered.
The "wires" issue is a red herring.

http://en.wikipedia.org/wiki/Red_herring

By "wire hiding" I mean that by using a single process
description using variables, there are only port inputs
and outputs in the logic description.
Everything goes in one box -- the entity.
There are no internal "directions" to worry about,
other than code going from the top to the bottom of the page.

In a multi-process description,
I have two or more process boxes inside the entity,
each with inputs and outputs.

I claim that not having to worry about connecting internal
"outputs" together in my description is a side benefit *for me*
of this description style.

-- Mike Treseler