Why does this if process wrong?

F

fl

Guest
Hi,

I write the following conditional decoder, but the synthesis gives error:

Line 240. parse error, unexpected EQ

from the first elsif line and thereafter elsif lines.

What is wrong?


Thanks,





signal tmp : unsigned(14 DOWNTO 0);

PROCESS(tmp)
BEGIN
if tmp(14) then
lut_reciprocal_internal <= o_tmp_6;
elsif (tmp(14 downto 13)=="01") then
lut_reciprocal_internal <= o_tmp_5;
elsif (tmp(14 downto 12)=="001") then
lut_reciprocal_internal <= o_tmp_4;
elsif (tmp(14 downto 11)=="0001") then
lut_reciprocal_internal <= o_tmp_3;
elsif (tmp(14 downto 10)=="00001") then
lut_reciprocal_internal <= o_tmp_2;
elsif (tmp(14 downto 9)=="000001") then
lut_reciprocal_internal <= o_tmp_1;
elsif (tmp(14 downto 9)=="000000") then
lut_reciprocal_internal <= o_tmp_0;
end if;
END PROCESS;
 
Thanks. The more difficult problem for me is the rest, such as:


elsif (tmp(14 downto 13)=="01") then


It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result.

I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again.


if tmp(14 downto 13) == 01 then
c_tmp_5 <= '1';
else
c_tmp_5 <= '0';
end if;
 
On Thursday, February 20, 2014 4:42:43 PM UTC-5, fl wrote:
Thanks. The more difficult problem for me is the rest, such as:





elsif (tmp(14 downto 13)=="01") then





It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result.



I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again.





if tmp(14 downto 13) == 01 then

c_tmp_5 <= '1';

else

c_tmp_5 <= '0';

end if;
Click to expand...

Thanks. I realize that VHDL needs one '=' sign for equal.
 
fl wrote:
Hi,

I write the following conditional decoder, but the synthesis gives error:

Line 240. parse error, unexpected EQ

from the first elsif line and thereafter elsif lines.

What is wrong?


Thanks,





signal tmp : unsigned(14 DOWNTO 0);

PROCESS(tmp)
BEGIN
if tmp(14) then
lut_reciprocal_internal <= o_tmp_6;
elsif (tmp(14 downto 13)=="01") then
lut_reciprocal_internal <= o_tmp_5;
elsif (tmp(14 downto 12)=="001") then
lut_reciprocal_internal <= o_tmp_4;
elsif (tmp(14 downto 11)=="0001") then
lut_reciprocal_internal <= o_tmp_3;
elsif (tmp(14 downto 10)=="00001") then
lut_reciprocal_internal <= o_tmp_2;
elsif (tmp(14 downto 9)=="000001") then
lut_reciprocal_internal <= o_tmp_1;
elsif (tmp(14 downto 9)=="000000") then
lut_reciprocal_internal <= o_tmp_0;
end if;
END PROCESS;
Click to expand...

if tmp(14) then

This sort of condition only works on booleans. Bit selects from an
unsigned wouldn't work unless you wrote something like:

if tmp(14) = '1' then

By the way, when you paste a snip of code it would be nice to
indicate where line 240 is.

--
Gabor
 
fl wrote:
On Thursday, February 20, 2014 4:42:43 PM UTC-5, fl wrote:
Thanks. The more difficult problem for me is the rest, such as:





elsif (tmp(14 downto 13)=="01") then





It looks like (tmp(14 downto 13)=="01") does not generate a Boolean result.



I try below to generate a Boolean. Unfortunately, it does not skip the same problem of two bits condition. How to generate a Boolean from other than 1 bit vector? Thanks again.





if tmp(14 downto 13) == 01 then

c_tmp_5 <= '1';

else

c_tmp_5 <= '0';

end if;

Thanks. I realize that VHDL needs one '=' sign for equal.
Click to expand...

I originally missed that, too. I do most of my coding in Verilog.

--
Gabor
 
Le 20/02/2014 21:55, fl a écrit :

signal tmp : unsigned(14 DOWNTO 0);

PROCESS(tmp)
BEGIN
if tmp(14) then
lut_reciprocal_internal <= o_tmp_6;
elsif (tmp(14 downto 13)=="01") then
lut_reciprocal_internal <= o_tmp_5;
elsif (tmp(14 downto 12)=="001") then
lut_reciprocal_internal <= o_tmp_4;
elsif (tmp(14 downto 11)=="0001") then
lut_reciprocal_internal <= o_tmp_3;
elsif (tmp(14 downto 10)=="00001") then
lut_reciprocal_internal <= o_tmp_2;
elsif (tmp(14 downto 9)=="000001") then
lut_reciprocal_internal <= o_tmp_1;
elsif (tmp(14 downto 9)=="000000") then
lut_reciprocal_internal <= o_tmp_0;
end if;
END PROCESS;
Click to expand...
Apart from the double = that you've already spotted, I think you don't
need to test all the upper 0s.
Assuming this is for synthesis, the only values you'll get are 0s and 1s
so you can test only one bit at a time :

if tmp(14) = '1' then
elsif tmp(13) = '1' then -- because tmp(14) is 0 if you reach this case.
elsif tmp(12) = '1' then ...
else
....
end if;

Nicolas
 
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