Why does ISE get angry with this shift register?

R

Richard Head

Guest
Ok Guys - heres some Verilog that ISE is spitting back at me with the following errors:

ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment


reg [`DataN:0] pixel1_pipe [3:0];

always @ (posedge clk)
begin
if (clken) begin

//THis is what I want to do, but it falls over with an error
//pixel1_pipe <= {pixel1_pipe[2:0], pixel1};

//This is what I have to do.
pixel2_pipe[0] <= pixel2;
pixel2_pipe[1] <= pixel2_pipe[0];
pixel2_pipe[2] <= pixel2_pipe[1];
pixel2_pipe[3] <= pixel2_pipe[2];

end
end

All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?
 
Richard Head <trickyhead@gmail.com> wrote:
Ok Guys - heres some Verilog that ISE is spitting back at me with the following errors:

ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment

;

always @ (posedge clk)
begin
if (clken) begin

//THis is what I want to do, but it falls over with an error
//pixel1_pipe <= {pixel1_pipe[2:0], pixel1};

//This is what I have to do.
pixel2_pipe[0] <= pixel2;
pixel2_pipe[1] <= pixel2_pipe[0];
pixel2_pipe[2] <= pixel2_pipe[1];
pixel2_pipe[3] <= pixel2_pipe[2];

end
end

All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?

Where is pixel2_pipe defined. I see the definition of pixel1_pipe but no use.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Uwe Bonnes wrote:
Richard Head <trickyhead@gmail.com> wrote:
Ok Guys - heres some Verilog that ISE is spitting back at me with the following errors:

ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment


reg [`DataN:0] pixel1_pipe [3:0];

always @ (posedge clk)
begin
if (clken) begin

//THis is what I want to do, but it falls over with an error
//pixel1_pipe <= {pixel1_pipe[2:0], pixel1};

//This is what I have to do.
pixel2_pipe[0] <= pixel2;
pixel2_pipe[1] <= pixel2_pipe[0];
pixel2_pipe[2] <= pixel2_pipe[1];
pixel2_pipe[3] <= pixel2_pipe[2];

end
end

All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?


Where is pixel2_pipe defined. I see the definition of pixel1_pipe but no use.

Bye
You can use a single dimension to work around this like:

reg [`DataN*4-1:0] pixel1_pipe;

.. . .
pixel1_pipe <= {pixel1_pipe, pixel1} ; // Upper bits are ignored
// anyway or you could write
// pixel1_pipe[`DataN*3-1:0]
// to avoid truncation warning
.. . .

and then for the Nth pipe: pixel1_pipe[`DataN*N +: `DataN];

-- Gabor
 

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