R
Richard Head
Guest
Ok Guys - heres some Verilog that ISE is spitting back at me with the following errors:
ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment
reg [`DataN:0] pixel1_pipe [3:0];
always @ (posedge clk)
begin
if (clken) begin
//THis is what I want to do, but it falls over with an error
//pixel1_pipe <= {pixel1_pipe[2:0], pixel1};
//This is what I have to do.
pixel2_pipe[0] <= pixel2;
pixel2_pipe[1] <= pixel2_pipe[0];
pixel2_pipe[2] <= pixel2_pipe[1];
pixel2_pipe[3] <= pixel2_pipe[2];
end
end
All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?
ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment
reg [`DataN:0] pixel1_pipe [3:0];
always @ (posedge clk)
begin
if (clken) begin
//THis is what I want to do, but it falls over with an error
//pixel1_pipe <= {pixel1_pipe[2:0], pixel1};
//This is what I have to do.
pixel2_pipe[0] <= pixel2;
pixel2_pipe[1] <= pixel2_pipe[0];
pixel2_pipe[2] <= pixel2_pipe[1];
pixel2_pipe[3] <= pixel2_pipe[2];
end
end
All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?