Which university produces good analog EEs?

Tim Williams · Oct 9, 2007

"Rich Grise" <rich@example.net> wrote in message
news

an.2007.10.09.00.07.12.375364@example.net...

Yeah - my last 20" just died recently, so I'm using a back-up
17". I tossed the 20", because it'd probably be cheaper to get
a new flat-screen than try to get it fixed. )-;

Neener, I'm on 21", at 1600x1200. But I'm so opulently rich with pixels
that I don't even have Outlook expanded to two-thirds of the screen ;-)

Tim

--
Deep Fryer: A very philosophical monk.
Website @ http://webpages.charter.net/dawill/tmoranwms

Fred Abse · Oct 9, 2007

On Mon, 08 Oct 2007 15:51:49 -0500, Spehro Pefhany wrote:

You need to add 3" to your monitor..

That's what these spam emails keep telling me ;-)

--
"Electricity is of two kinds, positive and negative. The difference
is, I presume, that one comes a little more expensive, but is more
durable; the other is a cheaper thing, but the moths get into it."
(Stephen Leacock)

krw · Oct 12, 2007

In article <gRAOi.68$0x7.56@newsfe05.lga>, tmoranwms@gmail.com
says...

"Rich Grise" <rich@example.net> wrote in message
newsan.2007.10.09.00.07.12.375364@example.net...
Yeah - my last 20" just died recently, so I'm using a back-up
17". I tossed the 20", because it'd probably be cheaper to get
a new flat-screen than try to get it fixed. )-;

Neener, I'm on 21", at 1600x1200. But I'm so opulently rich with pixels
that I don't even have Outlook expanded to two-thirds of the screen ;-)

36" at 3320x1050 here, though it takes two screens to do it. ;-)

--
Keith

krw · Oct 12, 2007

In article <LMrOi.55916$Um6.29015@newssvr12.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...

krw wrote:

In article <a2ucg35u48ig1q4kj8s061tki8cnihu41t@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...

On Thu, 4 Oct 2007 20:36:08 -0400, krw <krw@att.bizzzz> wrote:

In article <1c9Ni.5861$6p6.4832@newssvr25.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...

miso@sushi.com wrote:

[...]

Oh yeah, the lack of soldering skills. That would require the student
to have actually built something. These younguns just know how to
program. You've seen the posts where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right solution,
certainly over the discrete implementation you suggest.

I certainly would not say "vast". Many times I have pondered the use of
a uC in a design only to come to the conclusion that 50c is still too
expensive. It's amazing how cheap "poor-man's logic" can be.

You must have very small problems. I've never had one of those. ;-)
The project I'm working on now is in a pair of XC2V-6000s (my part)
and a couple of huge (don't know the model) Virtex-4s. I think I'm
only going to fill 5% of it (and fewer I/Os), but...

What's the most expensive FPGA you buy?

The most expensive I personally spec'ed was an SCX600E in, IIRC '99,
while they the Virtex-E family were still engineering prototypes.
They were $1200ea. As expensive as those things were, I had far more
invested in software to program them than the chips themselves.
Performance was an issue on that project.

I'm pretty sure the things I'm working on now are quite a bit more
than that; 10x the size, twice the pins, and rated for UncleS.

Seriously, I think you're only looking at a small niche. I do believe
uCs are the right solution for the vast majority. ...even the
birthday card I got has one in it. :-/

It's fun, now and then, to design for flat-out performance, and damn
the cost.

Often I've had projects where performance wasn't even the real issue.
Like I said, cost rarely, if ever, was.

The problem with using a uP in such projects is if you are designing a
chip, you need to know how to do it with gates as often that is the
smallest and lowest power solution. The ability to hand craft logic is
disappearing rapidly, but is very much needed in mixed mode chips
which are not done on fine geometry processes.

It sure is disappearing, just like analog skills seem to be almost gone
in fresh grad.

I've ripped out many uC solutions for reliability and cost reasons. Same
for PALs/GALs because that's the era back in the late 80's when
mixed/discrete design skills began to tank. The topper was a system
where I ripped out so many (plus went to 100% AC terminations) that the
power supply kept tripping off and one of them blew. We had managed to
get underneath the minimum load. IIRC the PALs was guzzling 30-40mA just
sitting there. Each.

What's the old saying? If they only learn how to use a hammer every
problem will begin to look like a nail. Heck, I've seen one-shots being
done with a uC. That almost made me sick.

One shots make me sick too. ;-)/2

What? Another case of asynchrophobia?

More acousticophobia, but I'm not a NASCAR fan either. They go off
in weeds. I don't like it when my designs do. It usually causes
long weeks (though I've been pulling 60hr weeks for a month or so).

Brace yourself for 70 hours or more if the universities don't start
cranking out engineers with more useful hardware knowledge.

Nah, I'm "retired". I picked up a contract job because I got bored,
this sounded like fun, and they pay well. ;-) I just got extended
until May, so I'll have something to keep me busy for the winter.
....and I'm out of the most leftist-weenie state in the union (my
house sold Monday)!

--
Keith

Jim Thompson · Oct 12, 2007

On Thu, 11 Oct 2007 19:27:56 -0400, krw <krw@att.bizzzz> wrote:

In article <LMrOi.55916$Um6.29015@newssvr12.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...
krw wrote:

In article <a2ucg35u48ig1q4kj8s061tki8cnihu41t@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...

On Thu, 4 Oct 2007 20:36:08 -0400, krw <krw@att.bizzzz> wrote:

In article <1c9Ni.5861$6p6.4832@newssvr25.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...

miso@sushi.com wrote:

[...]

Oh yeah, the lack of soldering skills. That would require the student
to have actually built something. These younguns just know how to
program. You've seen the posts where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right solution,
certainly over the discrete implementation you suggest.

I certainly would not say "vast". Many times I have pondered the use of
a uC in a design only to come to the conclusion that 50c is still too
expensive. It's amazing how cheap "poor-man's logic" can be.

You must have very small problems. I've never had one of those. ;-)
The project I'm working on now is in a pair of XC2V-6000s (my part)
and a couple of huge (don't know the model) Virtex-4s. I think I'm
only going to fill 5% of it (and fewer I/Os), but...

What's the most expensive FPGA you buy?

The most expensive I personally spec'ed was an SCX600E in, IIRC '99,
while they the Virtex-E family were still engineering prototypes.
They were $1200ea. As expensive as those things were, I had far more
invested in software to program them than the chips themselves.
Performance was an issue on that project.

I'm pretty sure the things I'm working on now are quite a bit more
than that; 10x the size, twice the pins, and rated for UncleS.

Seriously, I think you're only looking at a small niche. I do believe
uCs are the right solution for the vast majority. ...even the
birthday card I got has one in it. :-/

It's fun, now and then, to design for flat-out performance, and damn
the cost.

Often I've had projects where performance wasn't even the real issue.
Like I said, cost rarely, if ever, was.

The problem with using a uP in such projects is if you are designing a
chip, you need to know how to do it with gates as often that is the
smallest and lowest power solution. The ability to hand craft logic is
disappearing rapidly, but is very much needed in mixed mode chips
which are not done on fine geometry processes.

It sure is disappearing, just like analog skills seem to be almost gone
in fresh grad.

I've ripped out many uC solutions for reliability and cost reasons. Same
for PALs/GALs because that's the era back in the late 80's when
mixed/discrete design skills began to tank. The topper was a system
where I ripped out so many (plus went to 100% AC terminations) that the
power supply kept tripping off and one of them blew. We had managed to
get underneath the minimum load. IIRC the PALs was guzzling 30-40mA just
sitting there. Each.

What's the old saying? If they only learn how to use a hammer every
problem will begin to look like a nail. Heck, I've seen one-shots being
done with a uC. That almost made me sick.

One shots make me sick too. ;-)/2

What? Another case of asynchrophobia?

More acousticophobia, but I'm not a NASCAR fan either. They go off
in weeds. I don't like it when my designs do. It usually causes
long weeks (though I've been pulling 60hr weeks for a month or so).

Brace yourself for 70 hours or more if the universities don't start
cranking out engineers with more useful hardware knowledge.

Nah, I'm "retired". I picked up a contract job because I got bored,
this sounded like fun, and they pay well. ;-) I just got extended
until May, so I'll have something to keep me busy for the winter.
...and I'm out of the most leftist-weenie state in the union (my
house sold Monday)!

480)460-2350 | |
| E-mail Address at Website Fax

Jim Thompson · Oct 12, 2007

On Thu, 11 Oct 2007 19:27:56 -0400, krw <krw@att.bizzzz> wrote:

In article <gRAOi.68$0x7.56@newsfe05.lga>, tmoranwms@gmail.com
says...
"Rich Grise" <rich@example.net> wrote in message
newsan.2007.10.09.00.07.12.375364@example.net...
Yeah - my last 20" just died recently, so I'm using a back-up
17". I tossed the 20", because it'd probably be cheaper to get
a new flat-screen than try to get it fixed. )-;

Neener, I'm on 21", at 1600x1200. But I'm so opulently rich with pixels
that I don't even have Outlook expanded to two-thirds of the screen ;-)

36" at 3320x1050 here, though it takes two screens to do it. ;-)

480)460-2350 | |
| E-mail Address at Website Fax

krw · Oct 12, 2007

In article <7ictg3lsvpnukb3hkr1tnh03m7fgrfoi3f@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Thu, 11 Oct 2007 19:27:56 -0400, krw <krw@att.bizzzz> wrote:

In article <LMrOi.55916$Um6.29015@newssvr12.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...
krw wrote:

In article <a2ucg35u48ig1q4kj8s061tki8cnihu41t@4ax.com>,
jjlarkin@highNOTlandTHIStechnologyPART.com says...

On Thu, 4 Oct 2007 20:36:08 -0400, krw <krw@att.bizzzz> wrote:

In article <1c9Ni.5861$6p6.4832@newssvr25.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...

miso@sushi.com wrote:

[...]

Oh yeah, the lack of soldering skills. That would require the student
to have actually built something. These younguns just know how to
program. You've seen the posts where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right solution,
certainly over the discrete implementation you suggest.

I certainly would not say "vast". Many times I have pondered the use of
a uC in a design only to come to the conclusion that 50c is still too
expensive. It's amazing how cheap "poor-man's logic" can be.

You must have very small problems. I've never had one of those. ;-)
The project I'm working on now is in a pair of XC2V-6000s (my part)
and a couple of huge (don't know the model) Virtex-4s. I think I'm
only going to fill 5% of it (and fewer I/Os), but...

What's the most expensive FPGA you buy?

The most expensive I personally spec'ed was an SCX600E in, IIRC '99,
while they the Virtex-E family were still engineering prototypes.
They were $1200ea. As expensive as those things were, I had far more
invested in software to program them than the chips themselves.
Performance was an issue on that project.

I'm pretty sure the things I'm working on now are quite a bit more
than that; 10x the size, twice the pins, and rated for UncleS.

Seriously, I think you're only looking at a small niche. I do believe
uCs are the right solution for the vast majority. ...even the
birthday card I got has one in it. :-/

It's fun, now and then, to design for flat-out performance, and damn
the cost.

Often I've had projects where performance wasn't even the real issue.
Like I said, cost rarely, if ever, was.

The problem with using a uP in such projects is if you are designing a
chip, you need to know how to do it with gates as often that is the
smallest and lowest power solution. The ability to hand craft logic is
disappearing rapidly, but is very much needed in mixed mode chips
which are not done on fine geometry processes.

It sure is disappearing, just like analog skills seem to be almost gone
in fresh grad.

I've ripped out many uC solutions for reliability and cost reasons. Same
for PALs/GALs because that's the era back in the late 80's when
mixed/discrete design skills began to tank. The topper was a system
where I ripped out so many (plus went to 100% AC terminations) that the
power supply kept tripping off and one of them blew. We had managed to
get underneath the minimum load. IIRC the PALs was guzzling 30-40mA just
sitting there. Each.

What's the old saying? If they only learn how to use a hammer every
problem will begin to look like a nail. Heck, I've seen one-shots being
done with a uC. That almost made me sick.

One shots make me sick too. ;-)/2

What? Another case of asynchrophobia?

More acousticophobia, but I'm not a NASCAR fan either. They go off
in weeds. I don't like it when my designs do. It usually causes
long weeks (though I've been pulling 60hr weeks for a month or so).

Brace yourself for 70 hours or more if the universities don't start
cranking out engineers with more useful hardware knowledge.

Nah, I'm "retired". I picked up a contract job because I got bored,
this sounded like fun, and they pay well. ;-) I just got extended
until May, so I'll have something to keep me busy for the winter.
...and I'm out of the most leftist-weenie state in the union (my
house sold Monday)!

Congrats! Did you decide on TN or KY?

Thanks. Haven't decided. I've been in NE OH (well, OH is on the
way) since early August. My wife will come out when the house closes
next month. We're still trying to get things firmed up.

--
Keith

krw · Oct 12, 2007

In article <kdetg3dsv2qp15dfo8sttgmc6g4mrkpbe1@4ax.com>, To-Email-
Use-The-Envelope-Icon@My-Web-Site.com says...

On Thu, 11 Oct 2007 19:27:56 -0400, krw <krw@att.bizzzz> wrote:

In article <gRAOi.68$0x7.56@newsfe05.lga>, tmoranwms@gmail.com
says...
"Rich Grise" <rich@example.net> wrote in message
newsan.2007.10.09.00.07.12.375364@example.net...
Yeah - my last 20" just died recently, so I'm using a back-up
17". I tossed the 20", because it'd probably be cheaper to get
a new flat-screen than try to get it fixed. )-;

Neener, I'm on 21", at 1600x1200. But I'm so opulently rich with pixels
that I don't even have Outlook expanded to two-thirds of the screen ;-)

36" at 3320x1050 here, though it takes two screens to do it. ;-)

I have two 19" ViewSonic VA-912's side-by-side at 1280x1024.

VA912? They show this as digital signage.

Schematic on the left pane, simulation (Probe) results on the right.

I always work dual screen (they're too cheap at work and I'm lost),
even text editing. I have the document on the primary and the tools
on the secondary. I use my my laptop's display (1400x1050) on the
left with a Dell 2005FPW (1920x1050) on the center/right. I have
another graphics card in the docking station for my Viewsonic P95fb,
but I can't get it to work.

--
Keith

Oct 12, 2007

On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:

In article <1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article <1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...

snip

Oh yeah, the lack of soldering skills. That would require the student
to have actually built something. These younguns just know how to
program. You've seen the posts where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right solution,
certainly over the discrete implementation you suggest.

--
Keith

The problem with using a uP in such projects is if you are designing a
chip, you need to know how to do it with gates as often that is the
smallest and lowest power solution. The ability to hand craft logic is
disappearing rapidly, but is very much needed in mixed mode chips
which are not done on fine geometry processes.

If you're designing a chip you aren't going to be using a PIC, now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith

You don't get it. The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much sense.
Memory elements are part of the state machine design. You need a place
to store the present state.

krw · Oct 14, 2007

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...

On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article <1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article <1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...

snip

Oh yeah, the lack of soldering skills. That would require the student
to have actually built something. These younguns just know how to
program. You've seen the posts where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right solution,
certainly over the discrete implementation you suggest.

--
Keith

The problem with using a uP in such projects is if you are designing a
chip, you need to know how to do it with gates as often that is the
smallest and lowest power solution. The ability to hand craft logic is
disappearing rapidly, but is very much needed in mixed mode chips
which are not done on fine geometry processes.

If you're designing a chip you aren't going to be using a PIC, now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith

You don't get it.

It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much sense.
Memory elements are part of the state machine design. You need a place
to store the present state.

Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

--
Keith

JosephKK · Oct 14, 2007

krw krw@att.bizzzz posted to sci.electronics.design:

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...
On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article
1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article
1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...

snip

Oh yeah, the lack of soldering skills. That would require
the student to have actually built something. These
younguns just know how to program. You've seen the posts
where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right
solution, certainly over the discrete implementation you
suggest.

--
Keith

The problem with using a uP in such projects is if you are
designing a chip, you need to know how to do it with gates as
often that is the smallest and lowest power solution. The
ability to hand craft logic is disappearing rapidly, but is
very much needed in mixed mode chips which are not done on fine
geometry processes.

If you're designing a chip you aren't going to be using a PIC,
now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith

You don't get it.

It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much
sense. Memory elements are part of the state machine design. You
need a place to store the present state.

Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

It is indeed a poor way to design one, state diagrams and state charts
are much better methods. Discrete logic and memory may well be the
best implementation, however.

krw · Oct 15, 2007

In article <VZqQi.4599$Pv2.2187@newssvr23.news.prodigy.net>,
joseph_barrett@sbcglobal.net says...

krw krw@att.bizzzz posted to sci.electronics.design:

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...
On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article
1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article
1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...

snip

Oh yeah, the lack of soldering skills. That would require
the student to have actually built something. These
younguns just know how to program. You've seen the posts
where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.

For the vast majority of applications, a uC is the right
solution, certainly over the discrete implementation you
suggest.

--
Keith

The problem with using a uP in such projects is if you are
designing a chip, you need to know how to do it with gates as
often that is the smallest and lowest power solution. The
ability to hand craft logic is disappearing rapidly, but is
very much needed in mixed mode chips which are not done on fine
geometry processes.

If you're designing a chip you aren't going to be using a PIC,
now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith

You don't get it.

It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much
sense. Memory elements are part of the state machine design. You
need a place to store the present state.

Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

It is indeed a poor way to design one, state diagrams and state charts
are much better methods. Discrete logic and memory may well be the
best implementation, however.

Rarely. There is almost always a better way, more reliable, using
fewer components, cheaper. All that good stuff they pay us for,
instead of showing how clever we are by reusing an old EPROM and TTL
laying that is collecting dust.

--
Keith

Joerg · Oct 15, 2007

JosephKK wrote:

krw krw@att.bizzzz posted to sci.electronics.design:

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...
On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article
1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article
1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...
snip

Oh yeah, the lack of soldering skills. That would require
the student to have actually built something. These
younguns just know how to program. You've seen the posts
where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.
For the vast majority of applications, a uC is the right
solution, certainly over the discrete implementation you
suggest.
--
Keith
The problem with using a uP in such projects is if you are
designing a chip, you need to know how to do it with gates as
often that is the smallest and lowest power solution. The
ability to hand craft logic is disappearing rapidly, but is
very much needed in mixed mode chips which are not done on fine
geometry processes.
If you're designing a chip you aren't going to be using a PIC,
now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith
You don't get it.
It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much
sense. Memory elements are part of the state machine design. You
need a place to store the present state.
Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

It is indeed a poor way to design one, state diagrams and state charts
are much better methods. Discrete logic and memory may well be the
best implementation, however.

It may be the best way. Example why: Our pellet stove turned itself on
(!) in the middle of summer. Guess the folks who programmed its 8051
must have goofed up. If I have my druthers (and some time) I'll rip it
all out and design it around some 74HC chips.

--
Regards, Joerg

http://www.analogconsultants.com/

krw · Oct 16, 2007

In article <IxNQi.6348$Pv2.1363@newssvr23.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...

JosephKK wrote:
krw krw@att.bizzzz posted to sci.electronics.design:

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...
On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article
1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article
1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...
snip

Oh yeah, the lack of soldering skills. That would require
the student to have actually built something. These
younguns just know how to program. You've seen the posts
where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.
For the vast majority of applications, a uC is the right
solution, certainly over the discrete implementation you
suggest.
--
Keith
The problem with using a uP in such projects is if you are
designing a chip, you need to know how to do it with gates as
often that is the smallest and lowest power solution. The
ability to hand craft logic is disappearing rapidly, but is
very much needed in mixed mode chips which are not done on fine
geometry processes.
If you're designing a chip you aren't going to be using a PIC,
now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith
You don't get it.
It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much
sense. Memory elements are part of the state machine design. You
need a place to store the present state.
Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

It is indeed a poor way to design one, state diagrams and state charts
are much better methods. Discrete logic and memory may well be the
best implementation, however.

It may be the best way. Example why: Our pellet stove turned itself on
(!) in the middle of summer. Guess the folks who programmed its 8051
must have goofed up. If I have my druthers (and some time) I'll rip it
all out and design it around some 74HC chips.

There are some things were a spring and clockwork are a better design
too.

--
Keith

Joerg · Oct 21, 2007

krw wrote:

In article <IxNQi.6348$Pv2.1363@newssvr23.news.prodigy.net>,
notthisjoergsch@removethispacbell.net says...
JosephKK wrote:
krw krw@att.bizzzz posted to sci.electronics.design:

In article <1192159624.046987.143310@i13g2000prf.googlegroups.com>,
miso@sushi.com says...
On Oct 3, 5:08 pm, krw <k...@att.bizzzz> wrote:
In article
1191381789.178535.304...@57g2000hsv.googlegroups.com>,
m...@sushi.com says...

On Oct 1, 5:43 pm, krw <k...@att.bizzzz> wrote:
In article
1191229725.673736.51...@r29g2000hsg.googlegroups.com>,
m...@sushi.com says...
snip

Oh yeah, the lack of soldering skills. That would require
the student to have actually built something. These
younguns just know how to program. You've seen the posts
where a pic uP is the solutions to any
task, not a state machine comprised of memory elements and
combinational logic.
For the vast majority of applications, a uC is the right
solution, certainly over the discrete implementation you
suggest.
--
Keith
The problem with using a uP in such projects is if you are
designing a chip, you need to know how to do it with gates as
often that is the smallest and lowest power solution. The
ability to hand craft logic is disappearing rapidly, but is
very much needed in mixed mode chips which are not done on fine
geometry processes.
If you're designing a chip you aren't going to be using a PIC,
now
are you? Hint: you won't likely be using "memory elements" and
combinatorial logic to build state machines either.

--
Keith
You don't get it.
It is not I who is dense around here.

The schools are teaching pic solutions, not the
ability to design state machines. Your hint doesn't make much
sense. Memory elements are part of the state machine design. You
need a place to store the present state.
Discrete memory + logic is a piss-poor way to design state machines
these days. We weren't talking about integrated designs.

It is indeed a poor way to design one, state diagrams and state charts
are much better methods. Discrete logic and memory may well be the
best implementation, however.

It may be the best way. Example why: Our pellet stove turned itself on
(!) in the middle of summer. Guess the folks who programmed its 8051
must have goofed up. If I have my druthers (and some time) I'll rip it
all out and design it around some 74HC chips.

There are some things were a spring and clockwork are a better design
too.

Actually, in this case you could be right. The first pellet stoves had
mechanical timers. For some reason I've never heard a complaint from
their owners ...

--
Regards, Joerg

http://www.analogconsultants.com/

Ecnerwal · Oct 21, 2007

In article <jPOSi.13142$lD6.7219@newssvr27.news.prodigy.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:

Actually, in this case you could be right. The first pellet stoves had
mechanical timers. For some reason I've never heard a complaint from
their owners ...

And on that note:

http://www.thalia.org/humdec97.html

--
Cats, coffee, chocolate...vices to live by

Joerg · Oct 22, 2007

Ecnerwal wrote:

In article <jPOSi.13142$lD6.7219@newssvr27.news.prodigy.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:

Actually, in this case you could be right. The first pellet stoves had
mechanical timers. For some reason I've never heard a complaint from
their owners ...

And on that note:

http://www.thalia.org/humdec97.html

Marvelous!

--
Regards, Joerg

http://www.analogconsultants.com/

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