B
Brian Drummond
Guest
On Wed, 09 Jan 2013 04:59:25 -0800, Michael S wrote:
combinational processes anyway!
last couple of years they have started to gain any traction.
- Brian
Apparently it's an Altera tool. Yes I have, so far.On Jan 8, 3:02Â am, Brian Drummond <br...@shapes.demon.co.uk> wrote:
On Mon, 07 Jan 2013 10:47:43 -0800, jonesandy wrote:
Verilog has so many rabbit holes that look like they should work,
but don't, and if you don't use a separate linter, you'll never find
them.
Rabbit holes ... I like it! that was my impression on the brief look I
took at Verilog, and I have never had to use it (other than adding DDR2
memories to my VHDL projects).
From that I learn that so far you managed to avoid qsys.
I think it's a harmless addition, but I've never found a role forYesterday I looked (again) at VHDL-2008 additions.
I like few of them.
By comparison to 2 items above, (all) specification in sensitivity list
may look as minor addition, but until now those error-prone sensitivity
list were the main reason for me to avoid combinatorial processes
altogether. Now I can reconsider.
combinational processes anyway!
Understandable. They have been around since the 80s, but it's only in theWould also be nice to see an interface to proof tools, along the lines
of SPARK
I don't consider proof tools particularly useful.
last couple of years they have started to gain any traction.
- Brian