which commercial HDL-Simulator for FPGA?

[SynopsysFPGAexpress]

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

1) Aldec Active-HDL
+ great design-flow assistants (state-diagram, block-diagram,
waveform-diagram editing, export to PDF)
+ possibly faster than Modelsim/PE?
- no direct support in FPGA design-suites (Webpack/Quartus)
- Windoze only (can WINE 1.0 run it?)
- Systemverilog is almost but not quite usable ('package' not
supported?!?)
"less than $6000 for mixed-lang. VHDL+Verilog simulation"
(Note, that configuration is the most basic, doesn't have
SWIFT/Smartmodel)
[first year pepetual-license, yearly maint. is additional 20%/year]

2) Mentor Modelsim PE
+ currently more solid Systemverilog support than Active-HDL,
(but limited to design-constructs, no assertions/coverage)
+ de-facto industry standard,
direct integration into FPGA design-suites (Webpack/Quartus)
+ SWIFT/Smartmodel support (no extra cost if using mixed-HDL license)
- I really don't like the integrated waveform viewer
- Windoze only (can WINE 1.0 run it?)
"less than $10,000 for mixed-lang. VHDL+Verilog simulation"
[first year perpetual-license, yearly maint. is additional 20%/year]

3) FPGA-vendor OEM solution (usually a crippled Modelsim/PE)
+ cheapest
+ Altera Modelsim officially supports Linux (Xilinx does not)
+ Xilinx Modelsim has same level of (design construct) Systemverilog
support as Modelsim/PE, quite good actually
- limited capacity, deliberately slower runtime performance
- term-based only (no perpetual license for Xilinx/Altera?)
- no mixed-HDL (VHDL+Verilog) -- deal-killer for me...
"less than $1500 for 1-language, 1-year license"

If I only had to do 'abstract' RTL-design (algorithm proof, no
device-dependent instantiations...)

*4) gHDL, Icarus Verilog
+ free, open-source VHDL, Verilog
- emacs/gvim not included
- no mixed-HDL (VHDL+Verilog) sim

..............

Kidding aside, my real requirements:

1) I foresee mixed-HDL as a *requirement* for any serious consulting job.
(Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but
third-parties aren't.)

2) ASIC sign-off is obviously not a concern -- who's going to compete with a
professional turn-key bureau?

3) Design-size (capacity) is an unknown. For front-end (RTL) simulation, I
think even the OEM Modelsims are adequate. But for gate-level, that might
push them over the limit. It's interesting that even a 'budget' <$500
FPGA-board already has sufficient gate-capacity to overwhelm a
single-designer...progress!

3) validation/qualification with fpga vendor. I like Active-HDL's
user-interface more than Modelsim, but I can't escape the fact that
Modelsim/PE has wider industry endorsement. It's hard to argue with the
management types who're more interested in checkboxes than the less
tangibles (oh ... like ... employee productivity?)

Finally, I note the irony of Modelsim/Altera and Modelsim/Xilinx editions.
Altera Quartus-II supports Systemverilog synthesis, quite well, actually.
But Altera's Modelsim is based on the aging 6.1g version, which is
regrettably limited. Xilinx Webpack doesn't support Systemverilog, but
their Modelsim/XE is based on the more recent 6.3c codebase. I find it
useful for testbenching, though too many colleagues heckle me for my
systemverilog "religion." (I believe in it, and so should they.)

 

[Joseph H Allen]

In article <g3e8sk$ssv1@cnn.xsj.xilinx.com>,
Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:

... Modelsim is still the best, but you pay for a
lot of things you don't really need, and the waveform viewer could be
improved. That's where you spend 90% of your time during debugging so
it should be a little easier to use.

I've used vcs and currently have access to ncsim, so I've not bothered with
modelsim. However, recently I tried the free one which comes with Altera
web edition.

So in either of these, you typically simulate and have all signals dumped to
a huge output file (using $dumpvars(0); $dumpon; for vcs or $shm_open(...);
$shm_probe(..); for ncsim). Then you can explore the design hierarchy and
choose which signals to view in vcs -RPP or simvision. The same is true for
even icarus verilog with gtkwave.

However with modelsim it looks like there is no way to do this. Instead,
when you add a signal to the viewer in the GUI, it re-runs the entire
simulation to get the new signal. Am I missing something or is this really
how it works? I can't believe that it would really work this way.

(Also the crippled free modelsim is slower than icarus).

Has anyone tried to simulate Altera's IP with icarus? I'm thinking about
the .vo simulation model of the altmemphy DDR controller.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[Joseph H Allen]

In article <20080619124737.4526bf02@wolfenstein.jpl.nasa.gov>,
Jason Zheng <Xin.Zheng@jpl.nasa.gov> wrote:

Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf
"mydump.wlf", and you'll get similar results (just in a different
format). In my experience ncsim is faster than Modelsim, and of course
it carries a higher price tag.

This didn't work, but I eventually figured it out:

Start with an empty directory except for some verilog files you want to
simulate:

# Create work directory
vlib work

# Compile verilog files (vcom for vhdl)
vlog tb.v
vlog dut.v

# Simulate
vsim -do "log -r *; run -all; quit -f" work.tb

- this creates a vsim.wlf file with everything in it just
as you say.

Now try to view the waveform. If I try:

vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"

This brings up modelsim GUI and opens the waveform viewer window. All of
signals are in the viewer, and they're all empty.

But this does work:

vsim -view vsim.wlf -do "view wave; add wave *"

but it won't work after you have done the previous vsim -wlf command, vsim
-wlf does something to the .wlf file or sets something in an initialization
file somewhere. I had to re-run the simulation before "vsim -view ..." for
it to work.


BTW, I notice that if I do add

initial
begin
$dumpvars(0);
$dumpon;
...
end

vsim will generate a dump.vcd file, and I can use gtkwave to view it just
fine. I had thought this didn't work, I guess I was wrong or something
changed recently. Maybe I should just forget about using modelsim's
built-in viewer.

I notice that when the GUI is open, I can't also run a simulation on the
command line because there is only one license.

This is modelsim 6.1g which comes with Quartus 8.0 web edition running under
windows.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[SynopsysFPGAexpress]

"Mike Treseler" <mtreseler@gmail.com> wrote in message
news:4859F704.2040001@gmail.com...

SynopsysFPGAexpress wrote:
As commodity PC hardware and prouctivity applications deline in price,
EDA tools are as (relatively) expensive as ever, necessitating yet
another discussion of "Which simulator is right for me?"

This reads like a thinly veiled marketing survey.

It is, I apologize if I mislead anyone. I wanted to hear other people's
choices and
compare them to my situation.

Kidding aside, my real requirements:
Which part were you kidding about?

For gHDL and Icarus Verilog, I said "emacs/gvim not included." It was a
poor attempt at humor.

1) I foresee mixed-HDL as a *requirement* for any serious consulting job.
(Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but
third-parties aren't.)

The device vendors are only HDL-neutral because
they are selling device netlists, not source code.
Not a plus in my book.

That's something I didn't think about, and I checked Xilinx's website.
It turns out, some of their IP-blocks (Microblaze, PCIe, PPC440, etc.) use
a new 'SecureIP' format, and so far, only Modelsim is supported. That
doesn't bode well, either...

http://www.xilinx.com/support/answers/30481.htm

 

[HT-Lab]

"General Schvantzkopf" <schvantzkopf@yahoo.com> wrote in message
news:iIqdncpPC63KCsbVnZ2dnUVZ_jKdnZ2d@comcast.com...

On Wed, 18 Jun 2008 18:01:59 -0700, SynopsysFPGAexpress wrote:

As commodity PC hardware and prouctivity applications deline in price,
EDA tools are as (relatively) expensive as ever, necessitating yet
another discussion of "Which simulator is right for me?"

I've done some benchmarking on Verilog simulators.

Lies, damn lies and benchmarks

Here are the times for
running our regression suite on one of our cores.
I ran the test suite on
Cadence NCSim on CentOS5, Mentor's Questa on both CentOS5 and XP, and
Altera's Modelsim on CentOS5.

Benchmarking is very difficult and not only requires multiple designs and
knowing the environment inside out you also need to know what the simulator
is doing to your code. Verilog has the advantage(?) that you can tweak the
simulator to improve performance however, this might break some simulations.
(Un)fortunately this is not possible with VHDL which is far more stricter in
what you can do with the compiler. Using one core without mentioning how
you measured it, simulator/compiler settings, versions etc is not much use
IMHO.

The system is a 3GHz Core2 with 8G of DDR.
NC is the fastest but Questa on CentOS5 is close. Questa on XP is much
slower then it is on Linux.

I found the same.

The Altera ModelSim is dog slow which is to
be expected, I'm sure that Mentor has deliberately crippled it.

This is fully documented. I believe the OEM versions are about 40% of PE,
however, the problem is that after a certain number of lines it grinds to a
halt and becomes completely useless.

Hans
www.ht-lab.com

NC, Linux 0:06:34
Questa, Linux 0:07:15
Questa, XP 0:18:14
Altera ModelSim, Linux 1:00:13

 

[Joseph H Allen]

In article <485BC40E.3020008@gmail.com>,
Mike Treseler <mtreseler@gmail.com> wrote:

General Schvantzkopf wrote:

The Altera ModelSim is dog slow which is to
be expected, I'm sure that Mentor has deliberately crippled it.

NC, Linux 0:06:34
Questa, Linux 0:07:15
Questa, XP 0:18:14
Altera ModelSim, Linux 1:00:13


Thanks for taking the time to run the test
and for sharing the results.
Interesting that speed is roughly proportional
to the cost of the license.

While the oem version is "dog slow" in this lineup,
it is still quite useful for debugging rtl
when all the licenses are checked out.

-- Mike Treseler

It would be interesting to see Icarus in this list. Also Verilator...

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[Joseph H Allen]

In article <1radnX8dq9ywT8bVnZ2dnUVZ_sDinZ2d@comcast.com>,
General Schvantzkopf <schvantzkopf@yahoo.com> wrote:

On Fri, 20 Jun 2008 07:51:58 -0700, Mike Treseler wrote:

General Schvantzkopf wrote:

The Altera ModelSim is dog slow which is to be expected, I'm sure that
Mentor has deliberately crippled it.

NC, Linux 0:06:34
Questa, Linux 0:07:15
Questa, XP 0:18:14
Altera ModelSim, Linux 1:00:13


Thanks for taking the time to run the test and for sharing the results.
Interesting that speed is roughly proportional to the cost of the
license.

While the oem version is "dog slow" in this lineup, it is still quite
useful for debugging rtl when all the licenses are checked out.

-- Mike Treseler

What should be of most interest to anyone who is looking to buy a serious
simulator is the difference between Linux and XP. I ran the same version
of Questa on both Linux and XP with the same license. Questa runs three
times as fast on Linux as it does on XP. I'm pretty sure that the time
difference can be attributed to the performance of the Linux file system
(EXT3) vs the XP file system (NTFS). The real purpose of my investigation
was to compare various Virtualization tools. I gathered the numbers that
I posted before on the native OSes to give me a baseline. I then ran the
NC and Questa tests on VMware Server, VMware Workstation and KVM. When
using a virtual disk all of the VMs were only 5-10% slower then native,
KVM being the fastest. However if I used a host machine directory that
was accessed via NFS the performance dropped dramatically, about 2.5X for
VMware and 5X for KVM. VMware's shared folders were just as fast as
VMware's virtual disk performance i.e. about 10% slower then the native
performance. The NFS mounted host directory performance on VMware was
about the same as native XP performance which leads me to believe that
XP's problem is it's file system.

I wonder if it's core XP or if it's the filesystem itself. There's a
Windows-XP port of EXT2 available. It would be amusing if it was faster than
NTFS.

So was your virus scanner on during the simulation

The answer is to just use Linux.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

 

[SynopsysFPGAexpress]

Software C/C++ (and other programming languages, too) have been
doing this for YEARS. Microsoft calls its solution "intelliSense".
It's in Developer Studio (VC++/VC##, VB.net/etc.).

The first time you (sucessfully) compile the project's source-code,
the class/variable browser registers every user-defined identifier
(typedef, class, function, struct, union, built-in type int/float/char) with
the editor.

Then, as you type source-code, the browser pops up a 'helper'
box. For function-calls (including the C/C++/Windows standard
library), it shows the argument-names and their data-type. I guess
you could call it dynamic annotation. You can jump to the definition
of the object under the cursor, at any time. (For standard library calls,
this is less useful -- most of the compiler header-files are unreadable
jibberish.)

As long as we are talking about our "wish list", I would also like an
editor that was smart enough to complete words and sentences in my
HDL. There are any number of ways that a program can track what you
are doing and try to anticipate your actions as you type. For
example, if I am creating a clocked process and typing an assignment
for a signal or variable , it would be nice to have the software know
that it needs a definition and an initialization in the reset portion
of the process. So as soon as I enter the assignment, it would take
me to the appropriate spot for the definition and start it for me to
complete followed by the same for the initialization in the reset
section of the process.

If I am typing a "with" statement, I want the software to see the word
"with" and put the rest of the structure on the screen for me to fill
in the blanks. I find all the typing to be tedious and error prone,
not to mention that after all these years, I still don't have the
syntax memorized and keep a small stack of books by my elbow.

Yeah, intelliSense does this for many contexts.
Though it sounds like you additionally want some form of AutoCompletion,
combined with context-sensitive editing.

 

[SynopsysFPGAexpress]

"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:87bq1snxfw.fsf@pangea.home.gustad.com...

Kim Enkovaara <kim.enkovaara@iki.fi> writes:

Joseph H Allen wrote:

So in either of these, you typically simulate and have all signals
dumped to
a huge output file (using $dumpvars(0); $dumpon; for vcs or
$shm_open(...);
$shm_probe(..); for ncsim). Then you can explore the design hierarchy
and
choose which signals to view in vcs -RPP or simvision. The same is true
for
even icarus verilog with gtkwave.

In my mind this might work for small designs, but the huge amount of
signal logging slows down the simulation. I usually like to log just

I've used this methods for many years for large ASIC designs. It slows
down the simulation, but I find this much more effective than running
the simulation again. Also it's more cost effective to release the
expensive simulation license and use the cheaper waveform viewer for
debugging. You can even run the simulations during the night and have
the VPD (TRN, SST or whatever you prefer) files waiting for you the
next morning.

For e/Specman and Systemverilog-TB debugging, the Cadence/NCsim
doesn't log dynamic-objects to the TRN/SST file. So you pretty much
have to do most debugging interactively (if you want to see Systemverilog
objects/queues/dynamic-arrays, etc.), with the full license checkout of
the simulator.

I'm not sure how that compares to Mentor Questasim or Synopsys VCS.

 

[Mike Treseler]

SynopsysFPGAexpress wrote:

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

This reads like a thinly veiled marketing survey.

If you actually are a designer,
get a proto design ready,
order evals of each simulator
then try them and see for yourself.

Kidding aside, my real requirements:
Which part were you kidding about?

1) I foresee mixed-HDL as a *requirement* for any serious consulting job.
(Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but
third-parties aren't.)

The device vendors are only HDL-neutral because
they are selling device netlists, not source code.
Not a plus in my book.

-- Mike Treseler

 

[Muzaffer Kal]

On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"
<fpgas@sss.com> wrote:

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

Don't forget http://fintronic.com/home.html and
http://simucad.com/products/verilogSimulation/silos-x.html

I personally like Finsim (from Fintronic) a lot. It's a compiled
simulator and it's quite fast.

 

[Brian Drummond]

On Wed, 18 Jun 2008 23:38:42 -0700, Muzaffer Kal <kal@dspia.com> wrote:

On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"
fpgas@sss.com> wrote:

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

Don't forget http://fintronic.com/home.html and
http://simucad.com/products/verilogSimulation/silos-x.html

I personally like Finsim (from Fintronic) a lot. It's a compiled
simulator and it's quite fast.

Both appear to fail the OP's requirements (and mine);
they look to be Verilog only.

- Brian

 

On Jun 18, 11:38 pm, Muzaffer Kal <k...@dspia.com> wrote:

On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"

fp...@sss.com> wrote:
As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

Don't forgethttp://fintronic.com/home.htmlandhttp://simucad.com/products/verilogSimulation/silos-x.html

I personally like Finsim (from Fintronic) a lot. It's a compiled
simulator and it's quite fast.

I've been using Veritak, a low cost Veritak simulator. It has had
some bugs, but the author
is VERY quick to fix problems. A surprise - he is also VERY
responsive to requests for
new features or enhancements. I'm very pleased with his product.

John Providenza

 

[Kevin Neilson]

SynopsysFPGAexpress wrote:

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...
....

If you have Xilinx ISE 10.1, check out ISIM, which comes "free" with it.
It's much improved and may meet your needs and in future releases
should have better a better user interface. I don't think it currently
supports SystemVerilog, (and you are correct in propagating your
religion) but might soon. Modelsim is still the best, but you pay for a
lot of things you don't really need, and the waveform viewer could be
improved. That's where you spend 90% of your time during debugging so
it should be a little easier to use.
-Kevin

 

[Jason Zheng]

On Thu, 19 Jun 2008 19:27:10 +0000 (UTC)
jhallen@TheWorld.com (Joseph H Allen) wrote:

However with modelsim it looks like there is no way to do this.
Instead, when you add a signal to the viewer in the GUI, it re-runs
the entire simulation to get the new signal. Am I missing something
or is this really how it works? I can't believe that it would really
work this way.

Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf
"mydump.wlf", and you'll get similar results (just in a different
format). In my experience ncsim is faster than Modelsim, and of course
it carries a higher price tag.

Older versions of Modelsim also seems to stall after long simulations,
wehreas ncsim never gave me any problems.

--
Faster, faster, you fool, you fool!
-- Bill Cosby

 

[Patrick Dubois]

On 18 juin, 21:01, "SynopsysFPGAexpress" <fp...@sss.com> wrote:

As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

1) Aldec Active-HDL
+ great design-flow assistants (state-diagram, block-diagram,
waveform-diagram editing, export to PDF)
+ possibly faster than Modelsim/PE?
- no direct support in FPGA design-suites (Webpack/Quartus)
- Windoze only (can WINE 1.0 run it?)
- Systemverilog is almost but not quite usable ('package' not
supported?!?)
"less than $6000 for mixed-lang. VHDL+Verilog simulation"
(Note, that configuration is the most basic, doesn't have
SWIFT/Smartmodel)
[first year pepetual-license, yearly maint. is additional 20%/year]

One vote for Active-HDL. I briefly used Modelsim before we bought
Active-HDL and for me anyway, the Active-HDL interface is much better.
It's true that it's not officially supported by Xilinx but in practice
that really never caused too much of a problem.

I really like to create a schematic top level with blocks that are
either more schematics themselves or directly vhdl blocks. That way
it's much easier to see how everything connects together, it helps
comprehension. I don't quite understand why some people insist on
writing direct VHDL connections between blocks. It's a little bit like
insisting on writing pspice netlists for simulations instead of using
the schematic editor. Active-HDL converts schematics to vhdl code
anyway, so it's never too late to go back to vhdl-only code. The
resulting code will be very clean if you keep your top level free of
logic.

The state-machine editor in Active-HDL is another story. To me simple
state machines don't need to be represented by a diagram to be
understood. On the other hand, large ones are hard to represent in a
diagram. So in the end I only write vhdl state machines.

Patrick

 

[rickman]

On Jun 19, 2:35 pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:

SynopsysFPGAexpress wrote:
As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...
...

If you have Xilinx ISE 10.1, check out ISIM, which comes "free" with it.
It's much improved and may meet your needs and in future releases
should have better a better user interface. I don't think it currently
supports SystemVerilog, (and you are correct in propagating your
religion) but might soon. Modelsim is still the best, but you pay for a
lot of things you don't really need, and the waveform viewer could be
improved. That's where you spend 90% of your time during debugging so
it should be a little easier to use.
-Kevin

Apologies if you are a Xilinx person, but I tried their Web Pack
edition with the in house tools and the simulator really sucks... or
blows or something not so good. Although I didn't see any issues with
the simulation speed, the compile speed is pretty slow. I was using
it for a while when my design was pretty small and the compiles were
taking half a minute. Using Aldec Active HDL the compiles take a
second for a much larger design and the simulation speed is not bad
considering that it is "crippled"ware.

Xilinx seems committed to improving their in house sim. I posted
about in a news group and got a reply from one of the developers which
was almost apologetic and sincerely interested in what I found
lacking.

In the meantime I expect to stick with commercial packages. When I do
make the switch, it will likely be to an open source simulator.

Rick

 

[rickman]

On Jun 19, 6:10 pm, Patrick Dubois <prdub...@gmail.com> wrote:

On 18 juin, 21:01, "SynopsysFPGAexpress" <fp...@sss.com> wrote:



As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"

The contendors are ...

1) Aldec Active-HDL
+ great design-flow assistants (state-diagram, block-diagram,
waveform-diagram editing, export to PDF)
+ possibly faster than Modelsim/PE?
- no direct support in FPGA design-suites (Webpack/Quartus)
- Windoze only (can WINE 1.0 run it?)
- Systemverilog is almost but not quite usable ('package' not
supported?!?)
"less than $6000 for mixed-lang. VHDL+Verilog simulation"
(Note, that configuration is the most basic, doesn't have
SWIFT/Smartmodel)
[first year pepetual-license, yearly maint. is additional 20%/year]

One vote for Active-HDL. I briefly used Modelsim before we bought
Active-HDL and for me anyway, the Active-HDL interface is much better.
It's true that it's not officially supported by Xilinx but in practice
that really never caused too much of a problem.

I really like to create a schematic top level with blocks that are
either more schematics themselves or directly vhdl blocks. That way
it's much easier to see how everything connects together, it helps
comprehension. I don't quite understand why some people insist on
writing direct VHDL connections between blocks. It's a little bit like
insisting on writing pspice netlists for simulations instead of using
the schematic editor. Active-HDL converts schematics to vhdl code
anyway, so it's never too late to go back to vhdl-only code. The
resulting code will be very clean if you keep your top level free of
logic.

I use a purely HDL hierarchy. I find that top level schematics or
even low level schematics of large functions tend to end up being more
like a net list than a drawing anyway. You have pins with names X,Y,Z
connected to net R,S,T on page 1. On page 2 you have nets R,S,T
connected to another part with pin names A,B,C. Making it a drawing
doesn't add much in my opinion. Once I gave up hope for schematics
and embraced the HDL world, I found joy in a life of text files and
the infinite advantages they have in the land of version control!

The state-machine editor in Active-HDL is another story. To me simple
state machines don't need to be represented by a diagram to be
understood. On the other hand, large ones are hard to represent in a
diagram. So in the end I only write vhdl state machines.

I agree. Again a diagram can only offer a bit more here than can the
HDL text file, but I don't like using special tools that make the code
more difficult to port. Keeping it in HDL can work well and has all
of those text and portability advantages.

Rick

 

[General Schvantzkopf]

On Wed, 18 Jun 2008 18:01:59 -0700, SynopsysFPGAexpress wrote:

As commodity PC hardware and prouctivity applications deline in price,
EDA tools are as (relatively) expensive as ever, necessitating yet
another discussion of "Which simulator is right for me?"

I've done some benchmarking on Verilog simulators. Here are the times for
running our regression suite on one of our cores. I ran the test suite on
Cadence NCSim on CentOS5, Mentor's Questa on both CentOS5 and XP, and
Altera's Modelsim on CentOS5. The system is a 3GHz Core2 with 8G of DDR.
NC is the fastest but Questa on CentOS5 is close. Questa on XP is much
slower then it is on Linux. The Altera ModelSim is dog slow which is to
be expected, I'm sure that Mentor has deliberately crippled it.

NC, Linux 0:06:34
Questa, Linux 0:07:15
Questa, XP 0:18:14
Altera ModelSim, Linux 1:00:13

 

[Mike Treseler]

General Schvantzkopf wrote:

The Altera ModelSim is dog slow which is to
be expected, I'm sure that Mentor has deliberately crippled it.

NC, Linux 0:06:34
Questa, Linux 0:07:15
Questa, XP 0:18:14
Altera ModelSim, Linux 1:00:13

Thanks for taking the time to run the test
and for sharing the results.
Interesting that speed is roughly proportional
to the cost of the license.

While the oem version is "dog slow" in this lineup,
it is still quite useful for debugging rtl
when all the licenses are checked out.

-- Mike Treseler