What's wrong with this amplifier?

Paul Burridge · Sep 6, 2003

On Sat, 06 Sep 2003 13:29:27 GMT, "George R. Gonzalez"
<grg2@comcast.net> wrote:

Just then, lightning crackled over Mount Olympus and this big Zeus-like
voice rang forth: "How about you smelly old buggers go over to that big
sheep and try COUNTING the teeth?"

To which Allegoriclese replied: "It's easier to do it with SPICE even
if the answer's wrong."
--

"I believe history will be kind to me, since I intend
to write it." - Winston Churchill

Mike Engelhardt · Sep 6, 2003

Paul,

Just then, lightning crackled over Mount Olympus and this big
Zeus-like voice rang forth: "How about you smelly old
buggers go over to that big sheep and try COUNTING the teeth?"

To which Allegoriclese replied: "It's easier to do it with
SPICE even if the answer's wrong."

I have a reputation of periodically going through the labs
chasing people out to get back to work doing simulations.

--Mike

Jim Thompson · Sep 6, 2003

On Sat, 06 Sep 2003 13:29:27 GMT, "George R. Gonzalez"
<grg2@comcast.net> wrote:

Waay back when the world was young, there was a Golden Age in Greece.

[snip]
No, you're both wrong! , countered Dyspepsion-- if you squueze the SPICE'd
wine skin just right, you get visions of horses with no visible teeth, just
pure imaginary roots!

That must be answer, because it sounds so pure and fine! added Bodacious.

Just then, lightning crackled over Mount Olympus and this big Zeus-like
voice rang forth: "How about you smelly old buggers go over to that big
sheep and try COUNTING the teeth?"

But the Philosophers were by that time too far under the influence of the
SPICE'd wine and didnt hear or understand a thing.

ROTFLMAO!

There is no replacement for experience, but "Spicing" is sure a hell
of a lot faster than breadboarding; and I defy you to breadboard an
analog design containing 10,000 transistors.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Paul Burridge · Sep 7, 2003

On Sat, 06 Sep 2003 10:11:03 -0700, Jim Thompson
<Jim-T@golana-will-get-you.com> wrote:

There is no replacement for experience, but "Spicing" is sure a hell
of a lot faster than breadboarding; and I defy you to breadboard an
analog design containing 10,000 transistors.

Jim, would I be right in assuming (I'm probably not) that you don't
have to worry about strays when developing an IC?
--

"I believe history will be kind to me, since I intend
to write it." - Winston Churchill

Paul Burridge · Sep 7, 2003

On Sat, 6 Sep 2003 13:19:24 -0400, "Charles Schuler"
<charlesschuler@comcast.net> wrote:

OK, Paul ... now that I am getting a little better with LT Spice, your
circuit is showing one watt out at 40 MHz with a power gain of 14 dB into a
50 ohm load. I added the FD700 model, used a 50 ohm resistor in series with
the input voltage source and changed the collector resistor to 1 ohm. I
redesigned the collector circuit to match 113 ohms to 50 ohms at 40 MHz with
a Q of 10. The values are 3 uH, 2 uH and 13 pF and the collector choke is
25 uH. I'll be glad to email you the file if you like.

By all means do so, Charles. I'd be most interested to run your
circuit. Please remember to delete the spam-spoiler from my address,
though.

--

"I believe history will be kind to me, since I intend
to write it." - Winston Churchill

Jim Thompson · Sep 7, 2003

On Sun, 07 Sep 2003 02:11:37 +0100, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

On Sat, 06 Sep 2003 10:11:03 -0700, Jim Thompson
Jim-T@golana-will-get-you.com> wrote:

There is no replacement for experience, but "Spicing" is sure a hell
of a lot faster than breadboarding; and I defy you to breadboard an
analog design containing 10,000 transistors.

Jim, would I be right in assuming (I'm probably not) that you don't
have to worry about strays when developing an IC?

No you would not be (completely) right. The device models include
their strays (that's what AD, AS, PD, PS... are all about). But the
strays from the metalization (capacitance and resistance) are unknown.
After layout we do what is called back-annotation which calculates
these strays. The back-annotation netlist is added to the original
netlist and the simulations are re-run.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Robert Hickey · Sep 7, 2003

"Jim Thompson" <Jim-T@golana-will-get-you.com> wrote in message

Jim, would I be right in assuming (I'm probably not) that you don't
have to worry about strays when developing an IC?

No you would not be (completely) right. The device models include
their strays (that's what AD, AS, PD, PS... are all about). But the
strays from the metalization (capacitance and resistance) are
unknown.
After layout we do what is called back-annotation which calculates
these strays. The back-annotation netlist is added to the original
netlist and the simulations are re-run.

...Jim Thompson

Do you have to deal with stray inductance? Or only resistance &
capacitance?

The tools seem to be quite lacking there.

Robert

Jim Thompson · Sep 7, 2003

On Sun, 07 Sep 2003 07:36:36 GMT, "Robert Hickey" <robert@yahoo.com>
wrote:

"Jim Thompson" <Jim-T@golana-will-get-you.com> wrote in message

Jim, would I be right in assuming (I'm probably not) that you don't
have to worry about strays when developing an IC?

No you would not be (completely) right. The device models include
their strays (that's what AD, AS, PD, PS... are all about). But the
strays from the metalization (capacitance and resistance) are
unknown.
After layout we do what is called back-annotation which calculates
these strays. The back-annotation netlist is added to the original
netlist and the simulations are re-run.

...Jim Thompson

Do you have to deal with stray inductance? Or only resistance &
capacitance?

The tools seem to be quite lacking there.

Robert

480)460-2350 | |
| E-mail Address at Website Fax

Robert Hickey · Sep 7, 2003

"Jim Thompson wrote in message

After layout we do what is called back-annotation which
calculates
these strays. The back-annotation netlist is added to the
original
netlist and the simulations are re-run.

...Jim Thompson

Do you have to deal with stray inductance? Or only resistance &
capacitance?

The tools seem to be quite lacking there.

Robert

As Kevin notes, not usually, although the wirebonds can be quite a
hassle at higher frequencies. I think I've posted a wirebond model
with skin effect in the past.

...Jim Thompson

<shrug>

My first project at <mumble> had me struggling to get a redesign of an
amplifier to run at 10-13 GHz with acceptable performance. All I had
for a simulator was PSpice and an in-house Model for our MESFETs. I
made some custom fitted Models for circuit transitions (wirebonds
mostly) from measurements with a HP8510 Network analyzer and struggled
with the rest.

Most of the other circuits in the place were Cell Phone frequencies
and others up to about 5 GHz. Those they could model fairly well.

I was fairly new and I pushed some areas closer in Layout than I
should have but with no way to model the effects I lacked the
experience to "just know" not to do that.

Didn't work out all that well.

But on that project and many others, the lack of inductance parasitic
modeling was a real problem.

One could say that only HP ADS or Compact's tools should be used at
those frequencies but as Johnson said about the dog walking on it's
hind legs (paraphrased) "...the remarkable thing isn't that it does it
badly, the remarkable thing is that it does it at all" [1]. And for
circuits up to 5GHz they could do it fairly well.

Robert Hickey

[1] Though IIRC, he referred to Women Preachers in the same sentence.

Keith R. Williams · Sep 10, 2003

In article <3jmmlv0ovn4a0ikbp9u7mkmgdjjpqes4kr@4ax.com>, Jim-
T@golana-will-get-you.com says...

On Sun, 07 Sep 2003 07:36:36 GMT, "Robert Hickey" <robert@yahoo.com
wrote:

"Jim Thompson" <Jim-T@golana-will-get-you.com> wrote in message

Jim, would I be right in assuming (I'm probably not) that you don't
have to worry about strays when developing an IC?

No you would not be (completely) right. The device models include
their strays (that's what AD, AS, PD, PS... are all about). But the
strays from the metalization (capacitance and resistance) are
unknown.
After layout we do what is called back-annotation which calculates
these strays. The back-annotation netlist is added to the original
netlist and the simulations are re-run.

...Jim Thompson

Do you have to deal with stray inductance? Or only resistance &
capacitance?

The tools seem to be quite lacking there.

Robert

As Kevin notes, not usually, although the wirebonds can be quite a
hassle at higher frequencies. I think I've posted a wirebond model
with skin effect in the past.

They can also be a godsend! A few years ago I was responsible
for EMI pre-qualification for some PC hardware. We had one chip
that radiated like hell in a flip-chip package, yet was rather
tame in a wirebond (same chip, except for an added layer of metal
for the flip-chip space transformation). If the customer got the
flip-chips he wanted there would have been hell to pay after the
*attempt* at FCC certification.

--
Keith

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