P
Pouya D
Guest
Likewise for St1 and 1. I've searched the documentation for Modelsim
inside out and can't find any good reason why it writes the vale "0"
for some nets in my waveform and "St0" for others. I assume that St0
means strong0 and St1 means strong1. The manual says that 0 and 1
correspond to strong0 and strong1, so why doesn't it just use 0 and 1?
I know I can ask the wave to be viewed in binary radix, which removes
the St prefix on the values, but this is annoying to do...
Some of my nets are vectors, whose value appears like: "St0 St0 St0
St0", and when I ask for a binary radix instead of symbolic radix I
get "0 0 0 0". The spaces in the representation throw me off and are
quite annoying.
Does anyone know what causes this? I'm using Verilog for FPGA RTL
design so I really don't care about drive strengths.
Thank you,
Pouya
inside out and can't find any good reason why it writes the vale "0"
for some nets in my waveform and "St0" for others. I assume that St0
means strong0 and St1 means strong1. The manual says that 0 and 1
correspond to strong0 and strong1, so why doesn't it just use 0 and 1?
I know I can ask the wave to be viewed in binary radix, which removes
the St prefix on the values, but this is annoying to do...
Some of my nets are vectors, whose value appears like: "St0 St0 St0
St0", and when I ask for a binary radix instead of symbolic radix I
get "0 0 0 0". The spaces in the representation throw me off and are
quite annoying.
Does anyone know what causes this? I'm using Verilog for FPGA RTL
design so I really don't care about drive strengths.
Thank you,
Pouya