Wanted: LM-709 (Spice model) National Op-Amp

[Jim Thompson]

On Sun, 25 Sep 2005 22:28:27 +0200, "Helmut Sennewald"
<HelmutSennewald@t-online.de> wrote:

[snip]

Btw, PSPICE has become harder to use since Cadence switched
to the ORCAD schematic interface which is intended for PCB designs.
This is ok for PCBs but you will need more time to make a
schematic for SPICE.

[snip]

I don't understand your comment. As much as I despise Capture, as the
worst GUI creation ever known to man, it does interface to PSpice just
fine.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Helmut Sennewald]

"Jim Thompson" <thegreatone@example.com> schrieb im Newsbeitrag
news:2h2ej1pq0n4s2g701uaf9e9js6bmtcrfcg@4ax.com...

On Sun, 25 Sep 2005 22:28:27 +0200, "Helmut Sennewald"
HelmutSennewald@t-online.de> wrote:

[snip]

Btw, PSPICE has become harder to use since Cadence switched
to the ORCAD schematic interface which is intended for PCB designs.
This is ok for PCBs but you will need more time to make a
schematic for SPICE.

[snip]

I don't understand your comment. As much as I despise Capture, as the
worst GUI creation ever known to man, it does interface to PSpice just
fine.

Hello Jim,

My intention was to say that a schematic capture program intended
for a complex PCB-layout program adds complexity which isn't
required for a (P-)SPICE schematic.

Best regards,
Helmut

 

[Jim Thompson]

On Sun, 25 Sep 2005 22:44:56 +0200, "Helmut Sennewald"
<HelmutSennewald@t-online.de> wrote:

"Jim Thompson" <thegreatone@example.com> schrieb im Newsbeitrag
news:2h2ej1pq0n4s2g701uaf9e9js6bmtcrfcg@4ax.com...
On Sun, 25 Sep 2005 22:28:27 +0200, "Helmut Sennewald"
HelmutSennewald@t-online.de> wrote:

[snip]

Btw, PSPICE has become harder to use since Cadence switched
to the ORCAD schematic interface which is intended for PCB designs.
This is ok for PCBs but you will need more time to make a
schematic for SPICE.

[snip]

I don't understand your comment. As much as I despise Capture, as the
worst GUI creation ever known to man, it does interface to PSpice just
fine.


Hello Jim,

My intention was to say that a schematic capture program intended
for a complex PCB-layout program adds complexity which isn't
required for a (P-)SPICE schematic.

Best regards,
Helmut

That's why the "Simulation Only" designator you can place on
parts/pages that don't actually end up on the board, but are needed
for simulation.

But I still prefer "Schematics" as the PSpice frontend.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Paul Rako]

Well, let me explain why I decide what package to use based on the
layout package. I spent 25 years as a contractor/consultant. The
recent rate I charged was 80 to 100 dollars an hour. Believe me,
a client does not care about SPICE runs. He wants to see hardware,
little green boards. Only then does his blood-pressure drop. As
far as they are concerned even drawing a schematic seems silly as
well as the layout software. Maybe that is why so very many
companies seem to lose the schematic and layout files and want
me to improve or fix things with only a Gerber. Then it is off
to Protel (or some other package I tend not to enjoy) because it
can import a Gerber to the layout package and at least lets you
wing things from there.

Now in my mind the most important principle about ECAD is connectivity.
That what you draw on the schematic will show up as a flight line
in the rats nest and that any gate swaps or re-annotation done
in layout can be back-annotated. Having a separate SPICE schematic
violates this principle. Now you have something whose coherence is only
assured by human inspection.

Now I sure do appreciate the difficulty in making SPICE sources in a
schematic for layout or alternatively, connector parts for something
that will be SPICEed. And Jim, I think when people talk about the
the misery of using SPICE Orcad Capture it is the "occurances" vs
"instances" issues I mentioned. You are one of several hard-core
designers I have met that prefers PSPICE schematics to capture. There
are enough of you that Cadence still lets you download the PSPICE
capture program even for 10.5 release.

As to getting the board parasitics back, then you have to leave the
lumped element SPICE world and go to 2 or 3-D field solvers like
hyperlynx. This is generally referred to as signal integrity.
High-zoot hyperlynx that can handle lossy transmission lines is
48 grand or so. And good old Orcad has a hyperlynx output export,
even though Hyperlynx is now a Mentor tool.

Judging our test is just observing the schematic and what one has to
do to get good results. Pretty much just read the thread when
you get around to it and comment on the methodology and results.
We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff that
did not converge and will post that and bear the withering criticism
that I did something stupid or had a bad model. But the group has
to understand it is not just about convergence-- it is about
having the real board agree with the SPICE results.

Paul



Jim Thompson wrote:

On Sun, 25 Sep 2005 10:17:33 GMT, Paul Rako <sp_a_mpa_u_l@yahoo.com
wrote:

[snip]

Mr. (Dr./Prof?) Thompson:


"Mr.", I only have a MSEE.


What do you use? I hope it is not some proprietary thing
like Analog Devices' internal SPICE.


I use PSpice A/D v10.5, although I'm trying to make time to evaluate a
newcomer, TTSpiceWorks <http://www.trabucotechnologies.com/>. But it
seems, the older I get the busier I get ;-)


I hope you will serve as
judge jury and executioner in our little test.


What "little test" is it? I haven't been following this thread
closely.


And remember
everyone-- in my opinion we are mis-applying SPICE. The
acronym stands for "Simulation Program with Integrated
Circuit Emphasis" It is not SPBLE. Spible would be
"Simulation Program with Board-Level Emphasis".


Indeed.


This is
why there seems to be such passions aroused when us board
guys say we don't worship SPICE the way IC designers do.


In the IC world we "back-annotate" to add the strays that result from
layout. Do "board guys" have such a tool?


BTW, Dave Tamura in the CAD department at National rolled his
eyes when I told him I said Process and Modeling departments
cost 5 or 10 million dollars a year for a big semiconductor
company. He hinted that tens times those numbers is not
unheard of. He also said that his CAD department is also
involved in making sure the models conform to reality.


[snip]

And Win wonders why discrete MOSFET models are inadequate ;-)

...Jim Thompson

 

[Mike Engelhardt]

Paul,

...it's not very hard to understand why LTspice runs
faster and is more accurate then other/earlier SPICE
engines. I occasionally give 4hr seminars that explain
in some detail what one needs to do to make a better
SPICE engine[...]in the seminar, I demonstrate the
fantastically improved accuracy of the core LTspice
solvers and the corresponding improvements in simulation
speed with live simulation runs. Anyway those with
legitimate interest in LTspice can contact your local
LTC office and request when/where the next seminars
will be.

Well if you will have a garbage-posting dishonest creep
like me to your four-hour seminar I feel the least I can
do is attend. I'll talk to Gary Sapia in the local
sales office about the seminar. Thanks for the invite.
Look for the guy in the back row wearing a Nixon mask.

No, you misunderstood that as an invite. You have no
legitimate interest in LTspice. You are just an analog
applications guy working on Webench for National Sem.
and a liar posting garbage about me, LTspice and Linear's
beloved CEO emeritus. IC companies target LTspice
all the time, you're just another source of misleading
and dishonest comments. Please be hereby advised, you
are not permitted to attend any LTspice seminar.

--Mike

 

[Robert]

"Paul Rako" <sp_a_mpa_u_l@yahoo.com> wrote in message
newszHZe.67$sL3.17@newssvr13.news.prodigy.com...

Well, let me explain why I decide what package to use based on the
layout package. I spent 25 years as a contractor/consultant. The
recent rate I charged was 80 to 100 dollars an hour. Believe me,
a client does not care about SPICE runs. He wants to see hardware,
little green boards. Only then does his blood-pressure drop. As
far as they are concerned even drawing a schematic seems silly as
well as the layout software. Maybe that is why so very many
companies seem to lose the schematic and layout files and want
me to improve or fix things with only a Gerber. Then it is off
to Protel (or some other package I tend not to enjoy) because it
can import a Gerber to the layout package and at least lets you
wing things from there.

Now in my mind the most important principle about ECAD is connectivity.
That what you draw on the schematic will show up as a flight line
in the rats nest and that any gate swaps or re-annotation done
in layout can be back-annotated. Having a separate SPICE schematic
violates this principle. Now you have something whose coherence is only
assured by human inspection.

Now I sure do appreciate the difficulty in making SPICE sources in a
schematic for layout or alternatively, connector parts for something
that will be SPICEed. And Jim, I think when people talk about the
the misery of using SPICE Orcad Capture it is the "occurances" vs
"instances" issues I mentioned. You are one of several hard-core
designers I have met that prefers PSPICE schematics to capture. There
are enough of you that Cadence still lets you download the PSPICE
capture program even for 10.5 release.

As to getting the board parasitics back, then you have to leave the
lumped element SPICE world and go to 2 or 3-D field solvers like
hyperlynx. This is generally referred to as signal integrity.
High-zoot hyperlynx that can handle lossy transmission lines is
48 grand or so. And good old Orcad has a hyperlynx output export,
even though Hyperlynx is now a Mentor tool.

Judging our test is just observing the schematic and what one has to
do to get good results. Pretty much just read the thread when
you get around to it and comment on the methodology and results.
We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff that
did not converge and will post that and bear the withering criticism
that I did something stupid or had a bad model. But the group has
to understand it is not just about convergence-- it is about
having the real board agree with the SPICE results.

Paul

<Since material top posted am cutting out previous>

"Having a separate SPICE schematic

violates this principle. Now you have something whose coherence is only
assured by human inspection."

Why do you assume this?

Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert

 

[Paul Rako]

Never heard of such a thing. Please name one or two and I will look them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.

Paul

Robert wrote:

"Paul Rako" <sp_a_mpa_u_l@yahoo.com> wrote in message
newszHZe.67$sL3.17@newssvr13.news.prodigy.com...

Well, let me explain why I decide what package to use based on the
layout package. I spent 25 years as a contractor/consultant. The
recent rate I charged was 80 to 100 dollars an hour. Believe me,
a client does not care about SPICE runs. He wants to see hardware,
little green boards. Only then does his blood-pressure drop. As
far as they are concerned even drawing a schematic seems silly as
well as the layout software. Maybe that is why so very many
companies seem to lose the schematic and layout files and want
me to improve or fix things with only a Gerber. Then it is off
to Protel (or some other package I tend not to enjoy) because it
can import a Gerber to the layout package and at least lets you
wing things from there.

Now in my mind the most important principle about ECAD is connectivity.
That what you draw on the schematic will show up as a flight line
in the rats nest and that any gate swaps or re-annotation done
in layout can be back-annotated. Having a separate SPICE schematic
violates this principle. Now you have something whose coherence is only
assured by human inspection.

Now I sure do appreciate the difficulty in making SPICE sources in a
schematic for layout or alternatively, connector parts for something
that will be SPICEed. And Jim, I think when people talk about the
the misery of using SPICE Orcad Capture it is the "occurances" vs
"instances" issues I mentioned. You are one of several hard-core
designers I have met that prefers PSPICE schematics to capture. There
are enough of you that Cadence still lets you download the PSPICE
capture program even for 10.5 release.

As to getting the board parasitics back, then you have to leave the
lumped element SPICE world and go to 2 or 3-D field solvers like
hyperlynx. This is generally referred to as signal integrity.
High-zoot hyperlynx that can handle lossy transmission lines is
48 grand or so. And good old Orcad has a hyperlynx output export,
even though Hyperlynx is now a Mentor tool.

Judging our test is just observing the schematic and what one has to
do to get good results. Pretty much just read the thread when
you get around to it and comment on the methodology and results.
We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff that
did not converge and will post that and bear the withering criticism
that I did something stupid or had a bad model. But the group has
to understand it is not just about convergence-- it is about
having the real board agree with the SPICE results.

Paul



Since material top posted am cutting out previous

"Having a separate SPICE schematic

violates this principle. Now you have something whose coherence is only
assured by human inspection."


Why do you assume this?

Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert

 

[Paul Rako]

Mike:
Does this mean we can't be friends?

Oh well, let me assure you that your hot-headed
personality will not prevent me from singing the
praises of LTspice once someone can show me some
facts like solution time, convergence success and
conformance to real-world board results. Since
those results depend on the models I hope you can
convince somebody at LT to post A to D converter
models. I sure don't see them on the website.
So when I wrote:

That may be why National does not release A to D converter SPICE
models.
maybe analog's comment:
Or maybe they are a bunch of hacks who should swallow their pride
and sign up for an LTspice seminar.
Should be taken by LT IC designers as well. But if you

won't let me go to the seminar then I will
be a hack forever. Sigh.

And stop being so damn sensitive. If you think I
am hard on Swanson you should hear what I have to
say about Halla. And I don't work directly for
National anyway, I contract there. (But I do drink
beer with LT people so that should count for
something.)

Look, all I am trying to say is that board level
SPICE is far less useful to system-level designers
("just apps guys" in your parlance) then it is
to IC designers. I am not trying to be like my
pal Pease that says SPICE is useless. I am not
as smart as Bob and I need SPICE to calculate
closely spaced poles and to do worse-case tolerance
stackups on passive attenuator networks. But
kids who expect it to successfully predict the
performance of a complex signal chains are delusional.
When temperature effects and part corner-cases come
into play then counting on SPICE is really absurd
(board-level). Here is where I do agree with Bob:
A computer program, no matter how big and fancy
cannot replace human judgment and experience.

Hey Mike, I got a 64Mbyte USB stick at Arrowfest
from ST microcontrollers. Will you let me come
to the seminar if give it to you? Please? I
was just kidding about the Nixon mask. Sigh.

Paul



Mike Engelhardt wrote:

Paul,


...it's not very hard to understand why LTspice runs
faster and is more accurate then other/earlier SPICE
engines. I occasionally give 4hr seminars that explain
in some detail what one needs to do to make a better
SPICE engine[...]in the seminar, I demonstrate the
fantastically improved accuracy of the core LTspice
solvers and the corresponding improvements in simulation
speed with live simulation runs. Anyway those with
legitimate interest in LTspice can contact your local
LTC office and request when/where the next seminars
will be.

Well if you will have a garbage-posting dishonest creep
like me to your four-hour seminar I feel the least I can
do is attend. I'll talk to Gary Sapia in the local
sales office about the seminar. Thanks for the invite.
Look for the guy in the back row wearing a Nixon mask.


No, you misunderstood that as an invite. You have no
legitimate interest in LTspice. You are just an analog
applications guy working on Webench for National Sem.
and a liar posting garbage about me, LTspice and Linear's
beloved CEO emeritus. IC companies target LTspice
all the time, you're just another source of misleading
and dishonest comments. Please be hereby advised, you
are not permitted to attend any LTspice seminar.

--Mike

 

[Ken Smith]

In article <LdSZe.684$Fi3.327@newssvr29.news.prodigy.net>,
Paul Rako <sp_a_mpa_u_l@yahoo.com> wrote:

Never heard of such a thing. Please name one or two and I will look them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.
[....]

There are a couple of nice programs that will check your PCB layout
program's netlist output against the spice net list to find errors. They
use some tricks to relate the net names to each other so that they will
find nets that are broken into two sections and nets that are shorted.
They are free to download and I was going to give you the link but since
you top posted I decided not to.

Since material top posted am cutting out previous

"Having a separate SPICE schematic

violates this principle. Now you have something whose coherence is only
assured by human inspection."


Why do you assume this?

Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert

--
--
kensmith@rahul.net forging knowledge

 

[Paul Rako]

Is Top-Posting time or space based? Is it because my Thunderbird
client is set to reply first with your quotes underneath?

Geez, no 4 hour LT SPICE seminar and no LVS tools. Sigh.

Paul


Ken Smith wrote:

In article <LdSZe.684$Fi3.327@newssvr29.news.prodigy.net>,
Paul Rako <sp_a_mpa_u_l@yahoo.com> wrote:

Never heard of such a thing. Please name one or two and I will look them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.

[....]
There are a couple of nice programs that will check your PCB layout
program's netlist output against the spice net list to find errors. They
use some tricks to relate the net names to each other so that they will
find nets that are broken into two sections and nets that are shorted.
They are free to download and I was going to give you the link but since
you top posted I decided not to.



Since material top posted am cutting out previous

"Having a separate SPICE schematic


violates this principle. Now you have something whose coherence is only
assured by human inspection."


Why do you assume this?

Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert

 

[Jim Thompson]

On Mon, 26 Sep 2005 14:24:26 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

In article <LdSZe.684$Fi3.327@newssvr29.news.prodigy.net>,
Paul Rako <sp_a_mpa_u_l@yahoo.com> wrote:
Never heard of such a thing. Please name one or two and I will look them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.
[....]
There are a couple of nice programs that will check your PCB layout
program's netlist output against the spice net list to find errors. They
use some tricks to relate the net names to each other so that they will
find nets that are broken into two sections and nets that are shorted.
They are free to download and I was going to give you the link but since
you top posted I decided not to.


[snip]

Come on! Tell us!

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Chuck Harris]

Oh, be a pal and post the links!

-Chuck
Ken Smith wrote:

In article <LdSZe.684$Fi3.327@newssvr29.news.prodigy.net>,
Paul Rako <sp_a_mpa_u_l@yahoo.com> wrote:
Never heard of such a thing. Please name one or two and I will look them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.
[....]

Oh, be a pal and post the links!

-Chuck

There are a couple of nice programs that will check your PCB layout
program's netlist output against the spice net list to find errors. They
use some tricks to relate the net names to each other so that they will
find nets that are broken into two sections and nets that are shorted.
They are free to download and I was going to give you the link but since
you top posted I decided not to.

Oh, be a pal and post the links!

-Chuck

Since material top posted am cutting out previous

"Having a separate SPICE schematic

violates this principle. Now you have something whose coherence is only
assured by human inspection."

Why do you assume this?

Oh, be a pal and post the links!

-Chuck

Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert

Oh, be a pal and post the links!

-Chuck

Actually, just do a Google on the words: spice netlist checker
and you will get links to dozens of programs that should do the
trick.

-Chuck

 

[Paul Rako]

Chuck Harris wrote:

Oh, be a pal and post the links!

-Chuck
Ken Smith wrote:

In article <LdSZe.684$Fi3.327@newssvr29.news.prodigy.net>,
Paul Rako <sp_a_mpa_u_l@yahoo.com> wrote:

Never heard of such a thing. Please name one or two and I will look
them up.
As I keep saying over and over and over I am concenred with board-level
tools, not what is available for ICs.

[....]


Oh, be a pal and post the links!

-Chuck

There are a couple of nice programs that will check your PCB layout
program's netlist output against the spice net list to find errors.
They use some tricks to relate the net names to each other so that
they will find nets that are broken into two sections and nets that
are shorted. They are free to download and I was going to give you
the link but since you top posted I decided not to.


Oh, be a pal and post the links!

-Chuck

Since material top posted am cutting out previous

"Having a separate SPICE schematic

violates this principle. Now you have something whose coherence is
only
assured by human inspection."


Why do you assume this?


Oh, be a pal and post the links!

-Chuck


Aren't LVS or "Layout versus Schematics" tools known in your work?

Robert


Oh, be a pal and post the links!

-Chuck

Actually, just do a Google on the words: spice netlist checker
and you will get links to dozens of programs that should do the
trick.

-Chuck

I have looked at Tanner's tool and others and they all seemed
geared to IC design or comparing two SPICE schematics.
I can see how it would be easy to compare the net-list
outputs of two programs but us board guys have a specific
problem: After we lay out the board we re-annotate so
that the reference designators ascend from left to right
and top to bottom. Now there needs to be yet another tool
so that the SPICE schematic can be back annotated. Naw,
enough trouble in the world-- I prefer to stick with Orcad
or Pads or Electronics Workbench that can do the layout
against one schematic. I will keep looking at the listings.
I did not know this type of tool existed.

PS: Use Opera web browser and you can plug-in the aspell
spell-checker to spell check any text box in the browser.
Works great in Google Groups.

Got a hold of Jim Williams and he will get the article out
tonight from his files. He said there were several circuits.
This should be fun.

Paul

 

[analog]

Paul Rako wrote:

We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Hello Paul,

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

Regards -- analog

 

[Jim Thompson]

On Wed, 28 Sep 2005 19:34:48 -0700, analog <analog@ieee.org> wrote:

Paul Rako wrote:

We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Hello Paul,

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

Regards -- analog

I'm anxious to see them as well.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[analog]

Jim Thompson wrote:

analog wrote:
Paul Rako wrote:

We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

I'm anxious to see them as well.

I hope you aren't bating your breath, because after almost a week
of nothing, it sure looks like Paul Rako was all empty promise - in
other words, a loser troll.

I sure hope he gives me reason to take that back. I still would
love to have a look at the Jim Williams test circuit - or any other
legitimate circuit that supposedly gives spice convergence fits.

As mentioned earlier, my efforts over at the LTspice usersgroup on
Yahoo Groups in soliciting such a mythical beast have all come up
empty handed. In my experience, most convergence stubborn
simulations turn out to be examples of garbage in, garbage out.
I have *never* come across a meaningful simulation that didn't
converge or couldn't be made to converge in short order.

Regards -- analog

 

[Jim Thompson]

On Sat, 01 Oct 2005 14:43:39 -0700, analog <analog@ieee.org> wrote:

Jim Thompson wrote:
analog wrote:
Paul Rako wrote:

We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

I'm anxious to see them as well.

I hope you aren't bating your breath, because after almost a week
of nothing, it sure looks like Paul Rako was all empty promise - in
other words, a loser troll.

I sure hope he gives me reason to take that back. I still would
love to have a look at the Jim Williams test circuit - or any other
legitimate circuit that supposedly gives spice convergence fits.

As mentioned earlier, my efforts over at the LTspice usersgroup on
Yahoo Groups in soliciting such a mythical beast have all come up
empty handed. In my experience, most convergence stubborn
simulations turn out to be examples of garbage in, garbage out.
I have *never* come across a meaningful simulation that didn't
converge or couldn't be made to converge in short order.

Regards -- analog

Same here. EVERY simulation I've tried that failed initial
convergence either had no Ground (node 0), or was truly a screwed-up
circuit.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Kevin Aylward]

analog wrote:

Jim Thompson wrote:
analog wrote:
Paul Rako wrote:

We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

I'm anxious to see them as well.

I hope you aren't bating your breath, because after almost a week
of nothing, it sure looks like Paul Rako was all empty promise - in
other words, a loser troll.

I sure hope he gives me reason to take that back. I still would
love to have a look at the Jim Williams test circuit - or any other
legitimate circuit that supposedly gives spice convergence fits.


As mentioned earlier, my efforts over at the LTspice usersgroup on
Yahoo Groups in soliciting such a mythical beast have all come up
empty handed. In my experience, most convergence stubborn
simulations turn out to be examples of garbage in, garbage out.
I have *never* come across a meaningful simulation that didn't
converge or couldn't be made to converge in short order.

I have. On many occasions.

I have to disagree. Sure, by and large LTSpice does deal with
convergence very well. However, pretty much any Spice3/XSpice based
spice can have problems (EWB, CM, VisualSpice, Tina, etc.), especially
with cmos cascode current mirrors. I know. I have such a mythical
beastie *right now*. Tanner Spice also cannot converge on them.

These circuits are *real* circuits with no design faults. Most board
level design don't really deal with large transistor count, high
impedance circuits, and so don't usually came up against these sort of
problems. In ic design its the norm.

Kevin Aylward
informationEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Charlie Edmondson]

analog wrote:

Jim Thompson wrote:

analog wrote:

Paul Rako wrote:


We want to enter a schematic Jim Williams built many years go and
see how various SPICE packages do. I also have some PSPICE stuff
that did not converge and will post that and bear the withering
criticism that I did something stupid or had a bad model. But the
group has to understand it is not just about convergence -- it is
about having the real board agree with the SPICE results.

Please thank Jim Williams for passing along his test schematic and
post it here along with your own test circuits (or just email them
to me if size or format is an issue and I'll be happy to post them
for you over on alt.binaries.schematics.electronic). It's been a
few days now. Should we expect them tomorrow?

I'm anxious to see them as well.


I hope you aren't bating your breath, because after almost a week
of nothing, it sure looks like Paul Rako was all empty promise - in
other words, a loser troll.

I sure hope he gives me reason to take that back. I still would
love to have a look at the Jim Williams test circuit - or any other
legitimate circuit that supposedly gives spice convergence fits.

As mentioned earlier, my efforts over at the LTspice usersgroup on
Yahoo Groups in soliciting such a mythical beast have all come up
empty handed. In my experience, most convergence stubborn
simulations turn out to be examples of garbage in, garbage out.
I have *never* come across a meaningful simulation that didn't
converge or couldn't be made to converge in short order.

Regards -- analog
Hi All,

Well, I can say that I have seen several designs that thwarted PSpice
convergence, that I couldn't fix, but then, there were several common
characteristics...

First, liberal use of ABM models to represent some portion of the
device, like VSwitches for FETs, or Evalues to do DC to DC conversion,
or other simplifications in the circuit, usually with no representation
of the parasitics or other 'realities' inherent in the represented device.

Second, 'interesting' references to ground, often through high
resistances (or occasionally, low resistances) that confuse the issue of
where to reference the voltages. While these, in and of themselves,
shouldn't be fatal, it does make traking down the problem more
difficult. Also, you can get order-of-magnitude errors from them, as
you get very high currents and very low currents in the same simulation.

This is also what makes SMPS simulations so difficult. They often run
into dynamic range problems, as on the one hand they have very high
current sections, on the other, they have pico-amp sections in the
control logic. Spice only has so much dynamic range to play with, and
transients can 'overload' the simulator!

Charlie

 

[JosephKK]

Neil wrote:

Looking for a spice model or subcircuit netlist for the LM709 from
National semiconductor. I asked intusoft, cause they have a free model
service. I bought their entry level software ICAP/4 8.3.3 from a dealer
purchased in 2000. For reasons I won't mention, I was denied the
request from their sales department.

I was going to email National, but from what I read in Bob's book
"Troubleshooting Analog circuits" he doesn't like S.P.I.C.E.
and for good reason...........

Any help on this request would be great....

Thanks
Neil

I Googled for it using "LM709 spice model" and found on the first page of
results i found:
http://www.macs.ece.mcgill.ca/~rfic/EC2/SPICE_MODEL_LIB.htm

Does that serve your needs?
--
JosephKK