wait for, vhdl

[Ramya Murali]

signal a : std_logic;
p1 : process
begin
a<= '0';
wait for 5 ns;
a <= '1';
end process p1;

My questions are:

a) Is the process suspended when 'wait for' is encountered and resumed
when 'wait for' is satisfied? Hence, a sensitivity list is redundant
when 'wait for' is used in a process?

b) Will there be signal assignment when the process is suspended (as
opposed to the conventional signal assignment at the end of the
process)? i.e., @ 0 ns, a is 0 and @ 5 ns, a is 1;

 

[Alan Fitch]

On 23/06/12 01:30, Ramya Murali wrote:

signal a : std_logic;
p1 : process
begin
a<= '0';
wait for 5 ns;
a <= '1';
end process p1;

My questions are:

a) Is the process suspended when 'wait for' is encountered and resumed
when 'wait for' is satisfied? Hence, a sensitivity list is redundant
when 'wait for' is used in a process?

b) Will there be signal assignment when the process is suspended (as
opposed to the conventional signal assignment at the end of the
process)? i.e., @ 0 ns, a is 0 and @ 5 ns, a is 1;

Hi Ramya,


To answer your question a), a sensitivity list in brackets is illegal
when using wait inside the process. So signal a will be scheduled to
change to '1' the next time the process suspends.

However the process immediately executes a <= '0' after the statement
a<= '1' as it loops back to the top automatically, so the value will
never change to '1' as it will be overwritten.

Then when it hits the wait for 5 ns, it suspends, and a will update to
'0'. You will never see the value '1'.

You could write your process as
process
begin
a <= '1';
a <= '0';
wait for 5 ns;
end process;

if that makes it clearer.

Regarding b) the trick to understanding VHDL is to know that there is
only one kind of process which always suspends when it hits a wait. When
all processes in a model are suspended, that's when signals update.

If you write

process(a,b)
begin
c <= a and b;
end process;

that is equivalent to

process
begin
c<= a and b;
wait on a,b;
end process;

The full syntax of the wait statement is

wait [on sensitivitylist] [until booleancondition] [for timeout];


I hope this helps,

regards
Alan


--
Alan Fitch

 

[Enrik Berkhan]

Ramya Murali <ramya.murali.d@gmail.com> wrote:

signal a : std_logic;
p1 : process
begin
a<= '0';
wait for 5 ns;
a <= '1';
end process p1;

My questions are:

a) Is the process suspended when 'wait for' is encountered and resumed
when 'wait for' is satisfied? Hence, a sensitivity list is redundant
when 'wait for' is used in a process?

Actually, waits in a process - be it directly visible or in a procedure
called by the process - and process sensitivity lists are mutually
exclusive.

Further, a process sensitivity list is equivalent to a wait statement at
the end of the process using the same sensitivity list (or an
automatically constructed list in the case of VHDL-2008 'all').

b) Will there be signal assignment when the process is suspended (as
opposed to the conventional signal assignment at the end of the
process)? i.e., @ 0 ns, a is 0 and @ 5 ns, a is 1;

That 'conventional signal assignment at the end' is nothing else than the
update at the above mentioned implicit wait.

In your example there will be repeated assignments of '0', because there
is no implicit wait in a non-sensitivity-list-process. The process will
directly continue with "a <= '0'" after "a <= '1'", with '0' overwriting
'1'. The waveform will never change. Only transactions will be generated
on s1, but no events.

I assume what you want might be:

p1: process is
begin
a <= '0';
wait for 5 ns;
a <= '1';
wait for 5 ns;
end process p1;


Enrik

 

[Paul Uiterlinden]

Alan Fitch wrote:

When all processes in a model are suspended, that's when signals update.

In my opinion that is an unnecessary mystification, and I guess it is even
wrong. Maybe it is true for synthesisable VHDL, where signal assignments
never have an "after" clause.

A signal assignment creates an event (if at all) in the future. Without
an "after" specification the event is projected to happen after one delta
delay. With an "after" specification the event is projected to happen after
the specified time. And if that time happens to be zero, the event will
happen after one delta.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

 

[Alan Fitch]

On 27/06/12 11:31, Paul Uiterlinden wrote:

Alan Fitch wrote:


When all processes in a model are suspended, that's when signals update.

In my opinion that is an unnecessary mystification, and I guess it is even
wrong. Maybe it is true for synthesisable VHDL, where signal assignments
never have an "after" clause.

A signal assignment creates an event (if at all) in the future. Without
an "after" specification the event is projected to happen after one delta
delay. With an "after" specification the event is projected to happen after
the specified time. And if that time happens to be zero, the event will
happen after one delta.

I was trying to remedy the original poster's "conventional signal
assignment at the end of the process" statement, which I think is
misleading. It sounds to me like it can be misunderstood to mean one
process can end, and then another process will see the updated signal
value within the same delta.

I agree in the interests of simplicity I didn't talk about assignments
scheduled with a non-0 delay. But then I also didn't mention postponed
processes, transport delay, or the pulse rejection limit

regards
Alan

--
Alan Fitch