wacky clocking of 74HC4017 - help!

[David L. Jones]

budgie <budgie@nowhere.cantech.net.au> wrote in message news:<3f73c362.13864348@news.cantech.net.au>...

On Tue, 23 Sep 2003 03:12:14 GMT, budgie
budgie@nowhere.cantech.net.au> wrote:

(snip)

I have a bizarre clocking situation occurring with a 74HC4017 which is
being clocked from the PC parallel port.

(snip)

The thing that has got me .. er, puzzled, is that (as posted in
responses elsewhere) it is ONLY the first lo-hi transition after
reset release that causes the double-clocking effect. And as I am
still at the stage of single-stepping the software, the reset is gone
some seconds before the first lo-hi CP0 transition.

On Tue, 23 Sep 2003 12:20:34 +1000, Mike Harding
mike_harding1@nixspamhotmail.com> wrote:

Keep us informed of your progress please.

Will do, even it is totally embarassing.

red face
OK, the cause was definitely too slow a clock rise time.
/red face

But the weird bit is why it ONLY double-clocked from the "0" state
after reset was removed, and not on subsequent clocks. That still
hasn't found an explanation.

Completely weirdo.
I'd love to know what causes this, let us know if you turn up anything.

Dave