VHDL vs Verilog

[Brad]

I've read that Verilog is about three times as productive as VHDL. I
use VHDL, mostly because enumerated types are the crack that keeps me
addicted to VHDL. It seems to me that the two languages should be
equally productive, it's just that VHDL gives you more ways to step on
your dick. Any opinions on this?

-Brad

 

[General Schvantzkoph]

On Tue, 20 Apr 2010 08:46:13 -0700, Brad wrote:

I've read that Verilog is about three times as productive as VHDL. I use
VHDL, mostly because enumerated types are the crack that keeps me
addicted to VHDL. It seems to me that the two languages should be
equally productive, it's just that VHDL gives you more ways to step on
your dick. Any opinions on this?

-Brad

Verilog is concise which makes it easy to read and write, VHDL is
incredibly verbose. Verilog lacks the extensive type checking that VHDL
has but so what, there are lots of LINTing tools that do the job.

 

[Jonathan Bromley]

On Apr 20, 4:46 pm, Brad <hwfw...@gmail.com> wrote:

I've read that Verilog is about three times as productive as VHDL. I
use VHDL, mostly because enumerated types are the crack that keeps me
addicted to VHDL.

Have you felt the withdrawal symptoms when you try to
come off unconstrained subprogram arguments? I went
cold turkey for a while, but then my dealer lured me
back by reminding me that I could have a side order
of elaboration-time assertions, missing from Verilog
until 1800-2009, which is unobtainable on the streets.

Of course there are Verilog junkies out there too.
They get their fix from the nervous thrill of trying
to remember how to avoid race conditions, and their
flower-power highs from attempting to decipher other
people's code. And they have detox clinics with
LINT written in big letters over the front door.

========================================
Seriously: learn both (it's kinda useful for your
career anyhow) - not just superficially: get good
at them both - and then form your own judgment.
To echo another recent thread: my vote goes for
VHDL for RTL design, and SystemVerilog for testbench.
But there are many who would profoundly disagree.
--
Jonathan Bromley

 

[Amal]

On Apr 20, 12:42 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Apr 20, 4:46 pm, Brad <hwfw...@gmail.com> wrote:

I've read that Verilog is about three times as productive as VHDL. I
use VHDL, mostly because enumerated types are the crack that keeps me
addicted to VHDL.

Have you felt the withdrawal symptoms when you try to
come off unconstrained subprogram arguments?  I went
cold turkey for a while, but then my dealer lured me
back by reminding me that I could have a side order
of elaboration-time assertions, missing from Verilog
until 1800-2009, which is unobtainable on the streets.

Of course there are Verilog junkies out there too.
They get their fix from the nervous thrill of trying
to remember how to avoid race conditions, and their
flower-power highs from attempting to decipher other
people's code.  And they have detox clinics with
LINT written in big letters over the front door.

========================================
Seriously: learn both (it's kinda useful for your
career anyhow) - not just superficially: get good
at them both - and then form your own judgment.
To echo another recent thread: my vote goes for
VHDL for RTL design, and SystemVerilog for testbench.
But there are many who would profoundly disagree.
--
Jonathan Bromley

Very well said Jonathan. I have been a VHDL coder for a long time,
but I have been using Verilog for some time now and I still miss the
features that I cannot even have in Verilog. I too believe VHDL is
still the best for great RTL design, until a new committee improves
Verilog design features.

-- Amal

 

[haydin]

Here is an interesting read about the subject:
http://class.ee.iastate.edu/ee465/ee465s02/notes/billfuchs.pdf

And here is the original 1995 EETimes article which is mentioned in
the above PDF several times:
http://www.eetimes.com/editorial/1995/cooleycolumn9509.html


My recommendation for a beginner would be to start with Verilog, since
I believe the learning curve is not as steep as VHDL and you can
quickly get up to speed. As you get proficient with the tools, flows
and methodologies, you can start learning VHDL as well.

Hakan

Linera - www.linera.com.tr

 

[Jonathan Bromley]

On Apr 21, 8:33 am, haydin <hakan.ay...@gmail.com> wrote:

Here is an interesting read about the subject:
   http://class.ee.iastate.edu/ee465/ee465s02/notes/billfuchs.pdf

Of course, there is not a shred of bias nor of vested interest
in that article.... and, of course, it is totally up-to-date....

Many of its criticisms of VHDL for gate-level modelling were
amply justified back then, and still have some force today.
I don't think anyone is seriously suggesting that VHDL makes
as good a job of gate-level modelling as does Verilog. It's
at the level of RTL design that the contest remains active.

And here is the original 1995 EETimes article which is mentioned in
the above PDF several times:
   http://www.eetimes.com/editorial/1995/cooleycolumn9509.html

And, of course, there won't be even a trace of bigotry there....

I believe the learning curve is not as steep as VHDL and you can
quickly get up to speed.

This is the most staggering non sequitur. I think I agree that the
learning curve for Verilog is shallower, and therefore you can more
quickly get to some sort of result. But exactly that same shallow
learning curve means that your likely time to really good
proficiency is much longer. VHDL wears its challenges on its
sleeve; Verilog hides its difficulties behind a veneer of
simplicity. On your long but easy road to Verilog expertise,
you have plenty of time to practise-in your bad habits.
--
Jonathan Bromley

 

[Andy Peters]

On Apr 20, 8:46 am, Brad <hwfw...@gmail.com> wrote:

I've read that Verilog is about three times as productive as VHDL. I
use VHDL, mostly because enumerated types are the crack that keeps me
addicted to VHDL. It seems to me that the two languages should be
equally productive, it's just that VHDL gives you more ways to step on
your dick. Any opinions on this?

Actually, with VHDL you step on your dick. With Verilog, your
customers step on your dick. While wearing golf shoes.

-a

 

[Andy]

Add synthesizable fixed point and floating point data types and
operators to the many things that only VHDL can do without a change to
the language spec.

The amazing part to me is not the fixed/floating point itself, but the
simplicity with which it was created (again, without hacking the LRM)
in VHDL.

Andy