vhdl & verilog simulation

[alb]

Hi everyone,

I sadly found that my Actel Modelsim (10.1b) only supports single
language simulation (groan!) and I have some verilog modules that I need
to use in my vhdl testbench. The verilog modules are not synthesizable.

Any suggestion on how to proceed? I know there are some converters out
there but wanted to check whether there was any other potential path.

Thanks,

Al

--
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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[Rob Gaddi]

On Mon, 09 Sep 2013 23:53:57 +0200
alb <alessandro.basili@cern.ch> wrote:

Hi everyone,

I sadly found that my Actel Modelsim (10.1b) only supports single
language simulation (groan!) and I have some verilog modules that I need
to use in my vhdl testbench. The verilog modules are not synthesizable.

Any suggestion on how to proceed? I know there are some converters out
there but wanted to check whether there was any other potential path.

Thanks,

Al

--
A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

That was when I shelled out for a license for a paid simulator. Aldec
Active-HDL cost me $2K a year, and has generally been pretty worth it
versus the free version of ModelSim.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[HT-Lab]

On 09/09/2013 22:53, alb wrote:

Hi everyone,

I sadly found that my Actel Modelsim (10.1b) only supports single
language simulation (groan!) and I have some verilog modules that I need
to use in my vhdl testbench. The verilog modules are not synthesizable.

Any suggestion on how to proceed? I know there are some converters out
there but wanted to check whether there was any other potential path.

Thanks,

Al

Yes, unfortunately all OEM releases of Modelsim are single language.

If you don't use any Actel primitives you could try the free Xilinx ISIM
which is dual language.

It is a pity your Verilog modules are not synthesizable otherwise you
could have used a VHDL generated netlist out of Designer (or
Precision/Synplify). Converters are also out of the game because of this.

If you are working on a commercial product then I would suggest you bite
the bullet and get the commercial Modelsim+ version. It will save you a
lot of hassle. Also, if you look at the price of commercial simulators
against the cost of an engineer per day it doesn't look so bad any more.
Remember all prices are negotiable

Good luck,

Hans.
www.ht-lab.com

 

[alb]

On 10/09/2013 09:25, HT-Lab wrote:
[]

If you don't use any Actel primitives you could try the free Xilinx ISIM
which is dual language.

Unfortunately that is not the case, another reason why I hate vendor's
primitives... (but let me not continue with this rant!)

It is a pity your Verilog modules are not synthesizable otherwise you
could have used a VHDL generated netlist out of Designer (or
Precision/Synplify). Converters are also out of the game because of this.

This option indeed was also considered, I'm trying to profit of various
modules written for a verilog testbench which was intended for
simulation only.

I was looking specifically for a 1-wire slave model and after some
search I managed to find it. That said I'm a bit confused about why is
so complex to make a dual language simulation environment...

If you are working on a commercial product then I would suggest you bite
the bullet and get the commercial Modelsim+ version. It will save you a
lot of hassle. Also, if you look at the price of commercial simulators
against the cost of an engineer per day it doesn't look so bad any more.
Remember all prices are negotiable

The project is not commercial (it's a scientific payload), but your
considerations about costs do certainly apply also in this case.