VHDL Synchronization- two stage FF on all inputs?

rickman wrote:
On 12/15/2014 6:14 PM, GaborSzakacs wrote:
rickman wrote:
On 12/12/2014 5:05 PM, GaborSzakacs wrote:
rickman wrote:
On 12/12/2014 2:45 PM, GaborSzakacs wrote:
rickman wrote:
On 12/11/2014 9:08 AM, GaborSzakacs wrote:

[snip]


No. The second flip-flop has the same sort of metastable window as
the
first. If the first flop misses that window because the
metastability
was longer, then the second flop will resolve on the following clock
cycle. I think you may be under the misapprehension that the
metastable
state means that the first flop is outputing a "1/2" rather that "0"
or "1" logic level and any sampling during that time would cause
metastability in the second flop. In fact that's not the case.

I don't think that is correct. A metastable event can create all
sorts of problems on the output including oscillations and
indeterminate levels. These can produce metastability in the second
stage without having to hit a bullet with a bullet.



Think again. A flip-flop has positive feedback gain. Oscillation
is definitely not a possibility. Somewhere inside the flop you
could sit at a threshold voltage for a while, but once you start
to resolve, the swing will be monotonic. The next flop doesn't
get fed directly by the node sitting at its threshold, but from
a buffered copy. You'd need a buffer that oscillates when its
input sits near a threshold for a nanosecond or two. You won't
find anything like that in an FPGA.

There is some 40 years of experience and documentation showing the
effects of metastability. Please do a little research on the topic.

Rick,

If you had even started to look into some of that 40 years of
research, you may have come across a host of articles like this one:

http://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf



The only mention of oscillation is that it doesn't happen. At least
not at the output latch node.

This one says it can oscillate...
http://www.ganssle.com/articles/MetastabilityandFirmware.htm

This one does too...
http://a.vita.com/home/Learn/vmefaq/metastability.html

Another...
http://www-classes.usc.edu/engr/ee-s/552/coursematerials/ee552-G1.pdf

This one has pictures...
http://www.asic-world.com/tidbits/metastablity.html

You can talk about positive feedback, but that does not preclude
oscillations. With the appropriate condition such as the data input
changing at the right time just around the clock edge, both outputs of
the master FF (Q and Q not) can be in the same state. With
approximately equal delays in each gate, this condition will change to
both outputs changing to the opposite state, then back, etc until one of
the states "catches up" with the other and the circuit reaches a stable
state.

Some of the very earliest work analyzing the metastable state in digital
logic well documented oscillations in such circuits. Anyone who tells
you otherwise is talking through their hats.
Click to expand...

Any older ones? CMOS flip-flops built from transfer gates will not
oscillate. The only reputable instances I could find showing
oscillation referred to much older families that used cross-coupled
gates. Note that there are no "Q and Q not" outputs of a CMOS
flip-flop unless "Q not" is generated with an inversion after the
transfer gate latch. Cross-coupled gate implementations could
oscillate. You won't find those in an FPGA.
 
A simple thought on the topic, as it's often difficult to see the fores
for the trees:

When an asynchronous signal is sampled, there can be timing violations. N
number of chained FFs can give a _deterministic_ result. But they guarante
that it won't change between clock cycles and will look the same to al
connected inputs, whatever the value.

For example, a metastable reset could release some blocks one cycle befor
others, and the circuit is off to a bad start.

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 12/16/2014 11:58 AM, GaborSzakacs wrote:
rickman wrote:
On 12/15/2014 6:14 PM, GaborSzakacs wrote:
rickman wrote:
On 12/12/2014 5:05 PM, GaborSzakacs wrote:
rickman wrote:
On 12/12/2014 2:45 PM, GaborSzakacs wrote:
rickman wrote:
On 12/11/2014 9:08 AM, GaborSzakacs wrote:

[snip]


No. The second flip-flop has the same sort of metastable window as
the
first. If the first flop misses that window because the
metastability
was longer, then the second flop will resolve on the following clock
cycle. I think you may be under the misapprehension that the
metastable
state means that the first flop is outputing a "1/2" rather that "0"
or "1" logic level and any sampling during that time would cause
metastability in the second flop. In fact that's not the case.

I don't think that is correct. A metastable event can create all
sorts of problems on the output including oscillations and
indeterminate levels. These can produce metastability in the second
stage without having to hit a bullet with a bullet.



Think again. A flip-flop has positive feedback gain. Oscillation
is definitely not a possibility. Somewhere inside the flop you
could sit at a threshold voltage for a while, but once you start
to resolve, the swing will be monotonic. The next flop doesn't
get fed directly by the node sitting at its threshold, but from
a buffered copy. You'd need a buffer that oscillates when its
input sits near a threshold for a nanosecond or two. You won't
find anything like that in an FPGA.

There is some 40 years of experience and documentation showing the
effects of metastability. Please do a little research on the topic.

Rick,

If you had even started to look into some of that 40 years of
research, you may have come across a host of articles like this one:

http://webee.technion.ac.il/~ran/papers/Metastability-and-Synchronizers.IEEEDToct2011.pdf



The only mention of oscillation is that it doesn't happen. At least
not at the output latch node.

This one says it can oscillate...
http://www.ganssle.com/articles/MetastabilityandFirmware.htm

This one does too...
http://a.vita.com/home/Learn/vmefaq/metastability.html

Another...
http://www-classes.usc.edu/engr/ee-s/552/coursematerials/ee552-G1.pdf

This one has pictures...
http://www.asic-world.com/tidbits/metastablity.html

You can talk about positive feedback, but that does not preclude
oscillations. With the appropriate condition such as the data input
changing at the right time just around the clock edge, both outputs of
the master FF (Q and Q not) can be in the same state. With
approximately equal delays in each gate, this condition will change to
both outputs changing to the opposite state, then back, etc until one
of the states "catches up" with the other and the circuit reaches a
stable state.

Some of the very earliest work analyzing the metastable state in
digital logic well documented oscillations in such circuits. Anyone
who tells you otherwise is talking through their hats.


Any older ones? CMOS flip-flops built from transfer gates will not
oscillate. The only reputable instances I could find showing
oscillation referred to much older families that used cross-coupled
gates. Note that there are no "Q and Q not" outputs of a CMOS
flip-flop unless "Q not" is generated with an inversion after the
transfer gate latch. Cross-coupled gate implementations could
oscillate. You won't find those in an FPGA.
Click to expand...

If you are talking about the circuit shown in your reference it will
still oscillate the same way as a gate based FF. Each inverter in the
loop produces a signal, one is Q the other is Q not whether it is
labeled as such or not. Oscillations happen.

--

Rick
 
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