VHDL or Verilog?

[Rick C. Hodgin]

On Friday, June 23, 2017 at 4:04:57 AM UTC-4, Michael Kellett wrote:

Rick C. Hodgin:
On Thursday, June 22, 2017 at 5:13:02 AM UTC-4, David Brown wrote:
Have you considered other possibilities? VHDL and Verilog are the
two
main HDL languages, but they are far from the only choices...

To provide a little more detail, I know I've told you before that
I am going to author the Logician tool, which will allow a Blender
nodes-like ability to manipulate objects graphically, and to move
them in 3D space using OpenGL.

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I am a very visual person, and I have a hard time reading, and
despite my profession, that actually includes software code as
well. I prefer to draw things on white boards, on paper, to
have symbols used instead of words for things, etc. Also,
you've commented before on my unusual spacing in source files,
but I do that because another part of my brain is responsible
for organizing things geometrically, which relieves pressure on
my reading centers, making it easier for me to read.

So, my goals are to learn VHDL or Verilog, and then author the
Logician tool, and then have it translate the visual definition
of that tool into the VHDL or Verilog syntax language for use in
traditional tools. I do not plan to remain in VHDL or Verilog
for very long.

And for my immediate need, I'm getting conflicting guidance from
the group I've recently become involved with, and I just wanted
some advice from the FPGA group here. For the time being, I'll
be using Arduino to get my product working while I continue to
devote time to learning my Altera or Lattice FPGA toolkits in
the evenings and weekends.

-----
To all: I could use some assistance in working with Altera's
Quartus on a Cyclone V GX Starter Kit, or Lattice's
Diamond on an ECP5.

Thank you,
Rick C. Hodgin

Visual or graphic entry design tools for HDLs are somewhat out of favour
at the moment. (But not with me !) The only serious one I know (and use
every day) is the Block Diagram Editor in Aldec-HDL. If you want a tool
just to use you can buy that (Aldec-HDL Desktop edition) for about
Ł1600.

I'd be curious to see how it looks. I plan on mine being basically
this simple:

Note: I have not listened to the audio on this video, but
muted it and looked at the nodes illustration.

https://www.youtube.com/watch?v=Hro1BIWFEDQ&t=1m38s

If you want to create your own tool you will need some helpers -
it's more than a one man job.

I'll be sure to ask for helpers on the project.

There is a tool in Vivado but it's not really the same kind of thing.
I find the ability to describe a complex project with hierarchical block
diagrams to be very useful. Since the VHDl (or Verilog) is generated
from the diagrams you get customer friendly documentation that is
actually up to date !

I know when I sit down to think things through, it goes so much more
easily for me to think in concepts than in mechanics. I think the
visual tool will allow me to both.

But, I have several steps ahead of Logician in line:

Visual FreePro, Jr.
RDC and CAlive (compiler framework and C-like compiler)
Visual FreePro (full version)
ES/2 operating system (an open source OS/2 clone)
Logician
My various hardware designs

My long-term vision for completing these things are through
2025 if I can find revenue to allow me to devote my day labor
hours to these projects, and some help. Otherwise, it will
be a remainder-of-my-life kind of thing (I'm 47 now).

Thank you,
Rick C. Hodgin