[VHDL Documentation tool] First release of pyVhdl2Sch

[Laurent Cabaret]

Hi,

just a message to annouce the first release of a python based documentatiion tool.

pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file.
pyVhdl2Sch is based on Python and is a rewrite of the QT/Latex based Vhdl2Sch.

More details here :
https://github.com/LaurentCabaret/pyVhdl2Sch

Feel free to criticize/cheers/participate/...

Laurent

 

[Bart Fox]

pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file.
With a little fiddeling on MacOS X (with Macports) it run on my Mac too.

Nice work!

I did some changes to support signed/unsigned and std_ulogic as data types:

/pyVhdl2Sch$ git diff
diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py
index f9576ca..9933442 100644
--- a/file_manager/vhdl_reader.py
+++ b/file_manager/vhdl_reader.py
@@ -99,10 +99,10 @@ class Vhdl_reader:
if wire_type == "integer":
nb_wires = 32
else:
- if wire_type == "std_logic":
+ if wire_type == "std_logic" or wire_type == "std_ulogic":
nb_wires = 1
else:
- if wire_type == "std_logic_vector":
+ if wire_type == "std_logic_vector" or wire_type ==
"std_ulogic_vector" or wire_type == "signed" or wire_type == "unsigned":
bus_direction = real_words[5].lower()
bus_description = text.split("(")[1].split(")")[0]
if bus_direction == "downto":
diff --git a/pyV2S.py b/pyV2S.py
index 8cccdf0..ced8fd6 100755
--- a/pyV2S.py
+++ b/pyV2S.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python
# -*- coding: utf-8 -*-



Maybe you can enhance the skript to use the data type instead the number
of wires for unknown data types?
I use a lot of vhdl-recods defined in packages in my projects, so the
number of wires is difficult to determine.

regards,
Bart

 

[Dio Gratia]

On Thursday, August 28, 2014 7:53:10 PM UTC+12, Laurent Cabaret wrote:

pyVhdl2Sch is a documentation generator tool.

Feel free to criticize/cheers/participate/...

I noticed your tool doesn't accept the optional keyword signal in an interface signal declaration on the port.

interface_signal_declaration :: [ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ := static_expression ]

"Ports of any mode are also signals." As you can see the mode is optional and defaults to mode in.

Also a subtype indication can be more than a name and an index range:

subtype_indication :: [ resolution_indication ] type_mark [ constraint ]

resolution_indication :: resolution_function_name | ( element_resolution )

element_resolution ::= array_element_resolution | record_resolution

array_element_resolution ::= resolution_indication

record_resolution ::= record_element_resolution { , record_element_resolution }

record_element_resolution ::= record_element_simple_name resolution_indication

(These are from IEEE Std 1076-2008). A port signal can be a record, too.

A resolution indication can appear wherever there is a driver. This is valid VHDL code:

library ieee;
use ieee.std_logic_1164.all;

package a_pkg is

function x_res (to_resolve: std_logic_vector) return std_ulogic;

end a_pkg;

package body a_pkg is

function x_res (to_resolve: std_logic_vector) return std_ulogic is
variable r: std_ulogic;
begin
r := 'Z';
for i in to_resolve'range loop
r := r or to_resolve(i);
end loop;
return r;
end function x_res;

end a_pkg;

library ieee;
use ieee.std_logic_1164.all;
use work.a_pkg.all;

entity foo is
port (
signal a: in std_logic;
signal b: in std_logic;
signal c: in std_logic;
signal p: out x_res std_logic
);
end entity;

architecture fum of foo is

begin
p <= a;
p <= b;
p <= c;
end architecture;

As you can see there's a resolution function declared and because it's not an array type or a record type there are no parentheses for an array element resolution function. A record can have a resolution function for each record element, while there's only one for an array type.

I've written schematic symbol generators several times over the years what your program does isn't a surprise, the geometry familiar.

That you discard the subtype indication (index range) limits the use to block diagrams (for documentation). There's at least one PDF based schematic package out there (Kicad). It'd likely require your own PDF code generation to make symbols for it.

A three signal port entity generated a 10KB PDF file, you're own PDF code generation could possibly reduce that should you be able to live with a standard embedded font. The issue here is eventually swamping a word processor by including embedded PDF files accumulating in size. Open Office/Libre Office can slow down with a relatively few large image files, It's the redraw times.

We used to do a lot of PostScript code for this kind of stuff back in the day, PDF can be on par and schematic symbols are about as hard as printing overlays on bank checks. You could do PostScript and rely on conversion to PDF.

 

[Laurent Cabaret]

Le samedi 30 aoűt 2014 18:08:34 UTC+2, Bart Fox a écrit :

pyVhdl2Sch is a documentation generator tool. It takes VHDL files (.vhd) as entry and generates a pdf schematic for each input file.
With a little fiddeling on MacOS X (with Macports) it run on my Mac too.

Nice work!

I did some changes to support signed/unsigned and std_ulogic as data types:

/pyVhdl2Sch$ git diff
diff --git a/file_manager/vhdl_reader.py b/file_manager/vhdl_reader.py
index f9576ca..9933442 100644
--- a/file_manager/vhdl_reader.py
+++ b/file_manager/vhdl_reader.py
@@ -99,10 +99,10 @@ class Vhdl_reader:
if wire_type == "integer":
nb_wires = 32
else:
- if wire_type == "std_logic":
+ if wire_type == "std_logic" or wire_type == "std_ulogic":
nb_wires = 1
else:
- if wire_type == "std_logic_vector":
+ if wire_type == "std_logic_vector" or wire_type ==
"std_ulogic_vector" or wire_type == "signed" or wire_type == "unsigned":
bus_direction = real_words[5].lower()
bus_description = text.split("(")[1].split(")")[0]
if bus_direction == "downto":
diff --git a/pyV2S.py b/pyV2S.py
index 8cccdf0..ced8fd6 100755
--- a/pyV2S.py
+++ b/pyV2S.py
@@ -1,4 +1,4 @@
-#!/usr/bin/python
+#!/usr/bin/env python
# -*- coding: utf-8 -*-



Maybe you can enhance the skript to use the data type instead the number
of wires for unknown data types?
I use a lot of vhdl-recods defined in packages in my projects, so the
number of wires is difficult to determine.

regards,
Bart

Hi,

I inserted your interesting message as an issue in the github space.
I think i solved it.

Many Thanks,
Laurent

 

[Laurent Cabaret]

Hi,

I inserted your interesting message as an issue in the github space.
here is the current state of his resolution :
- Signals are now allowed in port definition
- Still working on resolution functions!
- cairocffi embed all fonts (even standard ones) so Jura seems to be smaller than times or helvetica.
- Not sure to understand the kicad part
- pyVhdl2Sch now support pdf/svg/ps/png output
Many Thanks,
Laurent


Le samedi 30 aoűt 2014 22:15:52 UTC+2, Dio Gratia a écrit :

On Thursday, August 28, 2014 7:53:10 PM UTC+12, Laurent Cabaret wrote:

pyVhdl2Sch is a documentation generator tool.

Feel free to criticize/cheers/participate/...

I noticed your tool doesn't accept the optional keyword signal in an interface signal declaration on the port.

interface_signal_declaration ::> [ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ := static_expression ]

"Ports of any mode are also signals." As you can see the mode is optional and defaults to mode in.

Also a subtype indication can be more than a name and an index range:

subtype_indication ::> [ resolution_indication ] type_mark [ constraint ]

resolution_indication ::> resolution_function_name | ( element_resolution )

element_resolution ::= array_element_resolution | record_resolution

array_element_resolution ::= resolution_indication

record_resolution ::= record_element_resolution { , record_element_resolution }

record_element_resolution ::= record_element_simple_name resolution_indication

(These are from IEEE Std 1076-2008). A port signal can be a record, too.

A resolution indication can appear wherever there is a driver. This is valid VHDL code:

library ieee;
use ieee.std_logic_1164.all;

package a_pkg is

function x_res (to_resolve: std_logic_vector) return std_ulogic;

end a_pkg;

package body a_pkg is

function x_res (to_resolve: std_logic_vector) return std_ulogic is
variable r: std_ulogic;
begin
r := 'Z';
for i in to_resolve'range loop
r := r or to_resolve(i);
end loop;
return r;
end function x_res;

end a_pkg;

library ieee;
use ieee.std_logic_1164.all;
use work.a_pkg.all;

entity foo is
port (
signal a: in std_logic;
signal b: in std_logic;
signal c: in std_logic;
signal p: out x_res std_logic
);
end entity;

architecture fum of foo is

begin
p <= a;
p <= b;
p <= c;
end architecture;

As you can see there's a resolution function declared and because it's not an array type or a record type there are no parentheses for an array element resolution function. A record can have a resolution function for each record element, while there's only one for an array type.

I've written schematic symbol generators several times over the years what your program does isn't a surprise, the geometry familiar.

That you discard the subtype indication (index range) limits the use to block diagrams (for documentation). There's at least one PDF based schematic package out there (Kicad). It'd likely require your own PDF code generation to make symbols for it.

A three signal port entity generated a 10KB PDF file, you're own PDF code generation could possibly reduce that should you be able to live with a standard embedded font. The issue here is eventually swamping a word processor by including embedded PDF files accumulating in size. Open Office/Libre Office can slow down with a relatively few large image files, It's the redraw times.

We used to do a lot of PostScript code for this kind of stuff back in the day, PDF can be on par and schematic symbols are about as hard as printing overlays on bank checks. You could do PostScript and rely on conversion to PDF.

 

[alb]

Hi Laurent,

Laurent Cabaret <laurent.cabaret@gmail.com> wrote:
[]

pyVhdl2Sch is a documentation generator tool. It takes VHDL files
(.vhd) as entry and generates a pdf schematic for each input file.

tried and got this:

Warning - a special port type is used or your entity is not well formated.
by default I used your type name as a wire name
Here is the official supported type list :
- integer
- natural
- positive
- signed
- std_logic
- std_logic_vector
- std_ulogic
- unsigned
Traceback (most recent call last):
File "./pyV2S.py", line 30, in <module>
reader = Vhdl_reader(filename, options)
File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 31, in __init__
self.parse_entity_part()
File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 141, in parse_entity_part
self.extract_wire(raw_line)
File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 166, in extract_wire
wire_type = vhdl_wire_words[3].lower()
IndexError: list index out of range

The vhdl synthesizes correctly and all ports are std_logic[_vector].

I'm actually very motivated for introducing these tools for
documentation purposes, especially considering the possibility to
include it in a LaTeX document.

Al

 

[alb]

Hi Laurent,

Laurent Cabaret <laurent.cabaret@gmail.com> wrote:
[]

pyVhdl2Sch is a documentation generator tool. It takes VHDL files
(.vhd) as entry and generates a pdf schematic for each input file.

Additionally this is what I get on the example provided in the repo:

debian@debianyVhdl2Sch-master$ ./pyV2S.py tb_None.vhd
Traceback (most recent call last):
File "./pyV2S.py", line 30, in <module>
reader = Vhdl_reader(filename, options)
File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 30, in __init__
self.parse_vhdl_file()
File "/home/debian/pkgs/pyVhdl2Sch-master/file_manager/vhdl_reader.py", line 118, in parse_vhdl_file
if real_words[locate_end + 1] == self.entity.name:
IndexError: list index out of range

Am I missing something?

Al