VHDL code error

[Youssef Ahmed]

Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else.

my code is this:
"library ieee;
use ieee.std_logic_1164.all;

package andpackage is
component and2 is
port (a, b: IN std_logic;
c: OUT std_logic);
end component and2;
end package andpackage;

entity circuit2 is
port (a, b, x, y: IN std_logic;
d: OUT std_logic);
end entity circuit2;

architecture mixed of circuit2 is
for gate: and2 use entity work.and2(and2);
signal c,z: std_logic;
begin
gate: and2 port map (a,b,c);
d <= c XOR z;
op: process (x,y) is
begin
z <= x OR y;
end process op;
end architecture mixed;"

i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance.

 

[KJ]

On Friday, April 11, 2014 9:29:59 AM UTC-4, Youssef Ahmed wrote:
You need to place the following...

library ieee;
use ieee.std_logic_1164.all;

....before both the package definition (where you have it now) AND before the entity definition. Packages and entities are considered 'primary design units'. Any libraries you want to include must be listed prior to each one.. The 'architecture' is considered a 'secondary design unit' which does not need yet another round of 'library ieee...' because it has been immediately preceded by the primary design unit.

Kevin Jennings

 

[alb]

Hi Youssef,
Youssef Ahmed <eng.youssef.hefny@gmail.com> wrote:
[]

i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier
"std_logic"." while the 3rd just says "VHDL Compiler exiting", any
help would be greatly appreciated, thanks in advance.

the information you are providing is not sufficient to spot the problem.
In order to compile the code the compiler should know *where* to look
for the ieee library and use the package you are referring to.

Do not focus only on the code, try to see if the environment you have is
setup properly. If possible, try to compile something you *know* should
work (like an example from a project tutorial of your tools [1] or
something you borrow from a colleague). Once you are sure your
environment is properly setup then you can focus on the code.

Al

[1] I think long ago I did the exercise for an Orcad project, something
like a Chebyshev filter...it failed miserably!!

 

[HT-Lab]

On 11/04/2014 14:29, Youssef Ahmed wrote:

Hello there, i'm new here so i dont know if this is on topic or should be placed somewhere else.

my code is this:
"library ieee;
use ieee.std_logic_1164.all;

package andpackage is
component and2 is
port (a, b: IN std_logic;
c: OUT std_logic);
end component and2;
end package andpackage;

library ieee;
use ieee.std_logic_1164.all;
use work.andpackage.all;

entity circuit2 is
port (a, b, x, y: IN std_logic;
d: OUT std_logic);
end entity circuit2;

architecture mixed of circuit2 is
-- for gate: and2 use entity work.and2(and2);
signal c,z: std_logic;
begin
gate: and2 port map (a,b,c);
d <= c XOR z;
op: process (x,y) is
begin
z <= x OR y;
end process op;
end architecture mixed;"

i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance.

Hope this help,

Hans
www.ht-lab.com

 

[alb]

Hi Andy,
Andy <jonesandy@comcast.net> wrote:

I have seen designs where each file contained a package, an entity and
its architecture. The package contained a component declaration
corresponding to the entity in that file.

The instantiating architecture would use the packages associated with
entities it will use, and the packages are guaranteed to be compiled
if the entities are compiled.

the main drawback is that you end up with a package for each component,
which is less useful as a package in the end. A possibility maybe is to
define a 'context' (vhdl-2008) and maintain the list of packages in
there.

This is probably the cleanest way of keeping component declarations
easily usable, yet in sync with their entities, that I have seen (if
you have to use components at all.)

Another would be to generate a package with component declarations
automatically from a list of entities. Emacs has keybindings to copy an
entity declaration and paste it as a component, maybe with a little bit
of lisp would be possible to generate an entire package with all
necessary components in the same way.