VHDl - A little help please

[Kai]

A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input
CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that
implements such a system. Compile and verify the functionality of the program with appropriate
test cases.

How do I write the statement for this ?
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented

I am able to write this in C and C++ programming but how do i that in VHDL?

 

[KJ]

On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote:

A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input
CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that
implements such a system. Compile and verify the functionality of the program with appropriate
test cases.

How do I write the statement for this ?
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented

I am able to write this in C and C++ programming but how do i that in VHDL?

Post your code in C and then I'm sure someone will translate it into VHDL

Kevin Jennings

 

[rickman]

On 11/5/2014 6:27 PM, Kai wrote:

A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input
CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that
implements such a system. Compile and verify the functionality of the program with appropriate
test cases.

How do I write the statement for this ?
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented

I am able to write this in C and C++ programming but how do i that in VHDL?

I'm old school. I think in terms of the logic. So I design the logic
in my head as I go along and code the VHDL to describe the hardware.
After all, HDL stands for hardware description language.

Can you picture the logic you would need to implement the above
requirements?

--

Rick

 

[alb]

Hi Kai,

Kai <cklaso@gmail.com> wrote:

A system has a 3-bit input D_IN which is read in at every positive
going edge of a clock input CLK. If the current D_IN is greater than
the previous D_IN by at least 2, a 3-bit output COUNT is incremented.
If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT
will not increase further, till it is reset by giving 0s at D_IN for 3
consecutive cycles. Write a VHDL program that implements such a
system. Compile and verify the functionality of the program with
appropriate test cases.

First of all I'd suggest you post with an editor that limits the amount
of columns to 78 chars since it eases the reading and increases the
likelihood to get an answer.

Forget about VHDL and think about the logic. Breakdown your
'specification' in semantic pieces: there are registers and
combinatorial elements and you may easily spot them.

COUNT is incremented when D_IN is greater than previous by 2 so you need
to store the previous and the current value in order to compare them and
trigger the condition for COUNT to increase. COUNT is another register
since it needs to store information between events. You need to count
how many times you have the condition that D_IN is 0 (here you go
another counter).

Once you have the elements you only need to put them together. I leave
this up to you since you are learning VHDL and you should make an effort
to get it done (no free lunch in here!). If you have problems with your
implementation than post the code and I'm sure you'll find some help.

Al

p.s.: tell your professor that the specification is not clear and
there's room for misunderstanding on the ALARM signal since it is not
stated whether can be asynchronous or should be registerd and there's no
condition for ALARM to be deasserted.

You'll find out in your career that most of the issues are traced back
in unclear specification of the interfaces!

 

[Anton Gunman]

On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote:

A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input
CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that
implements such a system. Compile and verify the functionality of the program with appropriate
test cases.

How do I write the statement for this ?
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented

I am able to write this in C and C++ programming but how do i that in VHDL?

Hello,

The code below was NOT TESTED, so it might have some errors.
The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly).

You will still need to write a nice testbench to test some of the cases

Cheers,
Anton.


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_module is
port (
clk : in std_logic;
reset : in std_logic;
din_i : in std_logic_vector(2 downto 0);
count_o : out std_logic_vector(2 downto 0);
alarm_o : out std_logic);
end my_module;

architecture rtl of my_module is
-- Note: you can replace these '1d, 2d' with an array
signal din_1d : std_logic_vector(2 downto 0) := (others => '0');
signal din_2d : std_logic_vector(2 downto 0) := (others => '0');
signal count : unsigned(2 downto 0) := (others => '0');
signal inc_count : std_logic := '0';
signal rst_count : std_logic := '0';
signal alarm : std_logic := '0';

begin -- rtl

---------------------------------------------------------------------------
-- Delay pipes, used to save the previous value(s)
---------------------------------------------------------------------------
delay_pipes : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
din_1d <= (others => '0');
din_2d <= (others => '0');
else
din_1d <= unsigned(din_i);
din_2d <= din_1d;
end if;
end if;
end process delay_pipes;

---------------------------------------------------------------------------
-- Count 'increment'
-- * Check that current value is > than previous (to avoid wraparound)
-- * Check that the difference is >= 2
-- Count and alarm 'reset'
-- * Check that the data is zero for 3 consecutive clock cycles.
---------------------------------------------------------------------------
inc_count <= '1' when (unsigned(din_i) > d) and
((unsigned(din_i) - din_1d) >= 2) else '0';
rst_count <= '1' when (din_i = "000" and din_1d = "000" and
din_2d = "000") else '0';

counter : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
count <= (others => '0');
alarm <= '0';
else
if rst_count = '1' then
-- Reset the count and the alarm
count <= (others => '0');
alarm <= '0';
elsif inc_count = '1' then
if count < 6 then
-- Saturate count at 6
count <= count + 1;
else
-- Set the alarm if count >= 6
alarm <= '1';
end if;

end if;
end if;
end if;
end process counter;

count_o <= std_logic_vector(count);
alarm_o <= alarm;

end rtl;

 

[rickman]

On 11/6/2014 10:55 AM, Anton Gunman wrote:

On Wednesday, November 5, 2014 6:27:22 PM UTC-5, Kai wrote:
A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input
CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When
COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase
further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that
implements such a system. Compile and verify the functionality of the program with appropriate
test cases.

How do I write the statement for this ?
If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output
COUNT is incremented

I am able to write this in C and C++ programming but how do i that in VHDL?

Hello,

The code below was NOT TESTED, so it might have some errors.
The purpose is just to demonstrate a way of implementing the requirements (I hope I understood them correctly).

You will still need to write a nice testbench to test some of the cases

Cheers,
Anton.


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_module is
port (
clk : in std_logic;
reset : in std_logic;
din_i : in std_logic_vector(2 downto 0);
count_o : out std_logic_vector(2 downto 0);
alarm_o : out std_logic);
end my_module;

architecture rtl of my_module is
-- Note: you can replace these '1d, 2d' with an array
signal din_1d : std_logic_vector(2 downto 0) := (others => '0');
signal din_2d : std_logic_vector(2 downto 0) := (others => '0');
signal count : unsigned(2 downto 0) := (others => '0');
signal inc_count : std_logic := '0';
signal rst_count : std_logic := '0';
signal alarm : std_logic := '0';

begin -- rtl

---------------------------------------------------------------------------
-- Delay pipes, used to save the previous value(s)
---------------------------------------------------------------------------
delay_pipes : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
din_1d <= (others => '0');
din_2d <= (others => '0');
else
din_1d <= unsigned(din_i);
din_2d <= din_1d;
end if;
end if;
end process delay_pipes;

---------------------------------------------------------------------------
-- Count 'increment'
-- * Check that current value is > than previous (to avoid wraparound)
-- * Check that the difference is >= 2
-- Count and alarm 'reset'
-- * Check that the data is zero for 3 consecutive clock cycles.
---------------------------------------------------------------------------
inc_count <= '1' when (unsigned(din_i) > d) and
((unsigned(din_i) - din_1d) >= 2) else '0';
rst_count <= '1' when (din_i = "000" and din_1d = "000" and
din_2d = "000") else '0';

counter : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
count <= (others => '0');
alarm <= '0';
else
if rst_count = '1' then
-- Reset the count and the alarm
count <= (others => '0');
alarm <= '0';
elsif inc_count = '1' then
if count < 6 then
-- Saturate count at 6
count <= count + 1;
else
-- Set the alarm if count >= 6
alarm <= '1';
end if;

end if;
end if;
end if;
end process counter;

count_o <= std_logic_vector(count);
alarm_o <= alarm;

end rtl;

You do realize you are doing his homework, right? Or it may even be a
test.

--

Rick