D
Daniel Kho
Guest
Dear all,
Recently I have built a small tool that eventually aims to give people the ability to code synthesisable designs in VHDL-2008. The new P1076-2008 standard has a whole bunch of new features that allow us to all write simple and concise designs. Many of us (me included) wouldn't want to go back to writing '93 code if we hadn't needed to. Unfortunately, current synthesis support for VHDL-2008 is still lacking in many EDA tools.
I like to change that, and hopefully many of you like to see better language support in tools as well. An alpha version of the tool can be found here:
http://www.tauhop.com (informational)
http://www.tauhop.com/#!hls (the tool)
Feel free to use it and test its features, currently limited to uninstantiated packages, generic packages, and generic types in packages. From the many requests I see in forums, I have decided that this is the area with which I should focus on right now: VHDL-2008's enhanced generics, before moving on to other features.
Please let me know if there are any other specific '2008 features you like me to spend some time on, and I will surely consider them to be added into my roadmap.
As many of you would understand, this effort is not trivial, and it does consume a significant amount of my time per week. At this time, you may use the service for free on www.tauhop.com/#!hls but I request your kind support in helping me bring food to the table, so I can continue working towards building something useful that all of you can use.
There are a number of options you can help me financially. The webpage gives you some options, but I also accept any arbitrary sum that you feel comfortable with. Just write to me (daniel.kho <at> tauhop.com) so we can work this out.
One more thing. If you feel you could help me market this product, please get in touch as well. You will have a good share of the revenue you help generate.
Best regards,
Daniel Kho
Tauhop Solutions
Recently I have built a small tool that eventually aims to give people the ability to code synthesisable designs in VHDL-2008. The new P1076-2008 standard has a whole bunch of new features that allow us to all write simple and concise designs. Many of us (me included) wouldn't want to go back to writing '93 code if we hadn't needed to. Unfortunately, current synthesis support for VHDL-2008 is still lacking in many EDA tools.
I like to change that, and hopefully many of you like to see better language support in tools as well. An alpha version of the tool can be found here:
http://www.tauhop.com (informational)
http://www.tauhop.com/#!hls (the tool)
Feel free to use it and test its features, currently limited to uninstantiated packages, generic packages, and generic types in packages. From the many requests I see in forums, I have decided that this is the area with which I should focus on right now: VHDL-2008's enhanced generics, before moving on to other features.
Please let me know if there are any other specific '2008 features you like me to spend some time on, and I will surely consider them to be added into my roadmap.
As many of you would understand, this effort is not trivial, and it does consume a significant amount of my time per week. At this time, you may use the service for free on www.tauhop.com/#!hls but I request your kind support in helping me bring food to the table, so I can continue working towards building something useful that all of you can use.
There are a number of options you can help me financially. The webpage gives you some options, but I also accept any arbitrary sum that you feel comfortable with. Just write to me (daniel.kho <at> tauhop.com) so we can work this out.
One more thing. If you feel you could help me market this product, please get in touch as well. You will have a good share of the revenue you help generate.
Best regards,
Daniel Kho
Tauhop Solutions