VHDL 2008 - how to declare 2nd dimension for array where 1st

[Tricky]

so I have this type definition:

type slv_array4_t is array(0 to 3) of std_logic_vector;

but when I try this:

signal some_thing : slv_array4_t(7 downto 0);

I get this error from VCOM:

ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained.

I get the same error when I try

signal some_thing : slv_array4_t(0 to 3)(7 downto 0);

It has no problem compiling the type delcaration.

So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?)

 

[Tricky]

On Wednesday, 20 August 2014 16:04:49 UTC+1, Tricky wrote:

so I have this type definition:



type slv_array4_t is array(0 to 3) of std_logic_vector;



but when I try this:



signal some_thing : slv_array4_t(7 downto 0);



I get this error from VCOM:



ERROR: In array constraint at depth 1 the array slv_array4_t has already been constrained.



I get the same error when I try



signal some_thing : slv_array4_t(0 to 3)(7 downto 0);



It has no problem compiling the type delcaration.



So whats the correct syntax for this? or should both dimension be unconstrained (and vcom should flag it?)

Sorry to bother you all - some light reading (2008 LRM) showed me it should be:

signal some_thing : slv_array4_t(open)(7 downto 0);