Verilog: Why the "maxcount" cannot keep its max value but ch

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Any Help Will Be Appreciated!

I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value.

The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count)

Is there any logical error? Or is there any Verilog Error that I missed?

Thank you very much!

module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2);
input Clock, Reset;
input signed [3:0] pt_0, pt_1, pt_2, pt_3;
output [6:0] hex1, hex0, hex3, hex2;

wire signed [6:0] count;
wire signed [6:0] maxcount;
score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);

display(count, maxcount, hex1, hex0, hex3, hex2);

endmodule

module display (count, maxcount, hex1, hex0, hex3, hex2);
input [6:0] count, maxcount;
output [6:0] hex1, hex0, hex3, hex2;

wire [4:0] unit, unit_m;
wire [4:0] tens, tens_m;

assign unit = count % 10;
assign tens = count / 10;

assign unit_m = count % 10;
assign tens_m = count / 10;

seg7 ud (unit, hex0);
seg7 td (tens, hex1);
seg7 umd (unit_m, hex2);
seg7 tmd (tens_m, hex3);


endmodule

module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);
input Clock, Reset;
//input signed [3:0] sum;
input [3:0] pt_0, pt_1, pt_2, pt_3;
parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110;
//input zero, negative, carry, overflow;

output signed [6:0] count, maxcount;
reg signed [6:0] count, maxcount;

////wire PS;
//reg NS;

always @(posedge Clock)
if (Reset) begin
count <= 7'b0;
maxcount <= 7'b0;
end else begin
if (count > maxcount) begin
maxcount <= count;
end
if (pt_0 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_0;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_1 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_1;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_2 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_2;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_3 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_3;
if (count > 7'b100010) begin
count <= 7'b0;
end
end
end
endmodule
 
I'm not an expert in Verilog, but I don't see anything obvious in the
code. I do see two possible issues. One is that maxcount is passed
into display, but not used for anything. Are unit_m and tens_m supposed
to be updated from maxcount? Is that where you are checking the value
of maxcount? The other is that maxcount is declared as both an output
and a reg. In VHDL that does not work. Is that ok in Verilog?

Rick


On 5/30/2014 9:53 PM, kaiyutony@gmail.com wrote:
Any Help Will Be Appreciated!

I wrote this module in order to keep track of the score (<= 99) for a game written in verilog and runs on a LED Array. I want it to be able to maintain a max score. When the current count is greater than maxcount, the maxcount will be equal to the current count, else it keeps its value.

The Problem is, I do not know why the maxcount changes its value whenever count changes (It cannot keep its value when count is less, but instead become less along with the count)

Is there any logical error? Or is there any Verilog Error that I missed?

Thank you very much!

module score_keep(Clock, Reset, pt_0, pt_1, pt_2, pt_3, hex1, hex0, hex3, hex2);
input Clock, Reset;
input signed [3:0] pt_0, pt_1, pt_2, pt_3;
output [6:0] hex1, hex0, hex3, hex2;

wire signed [6:0] count;
wire signed [6:0] maxcount;
score_counter sc (Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);

display(count, maxcount, hex1, hex0, hex3, hex2);

endmodule

module display (count, maxcount, hex1, hex0, hex3, hex2);
input [6:0] count, maxcount;
output [6:0] hex1, hex0, hex3, hex2;

wire [4:0] unit, unit_m;
wire [4:0] tens, tens_m;

assign unit = count % 10;
assign tens = count / 10;

assign unit_m = count % 10;
assign tens_m = count / 10;

seg7 ud (unit, hex0);
seg7 td (tens, hex1);
seg7 umd (unit_m, hex2);
seg7 tmd (tens_m, hex3);


endmodule

module score_counter(Clock, Reset, pt_0, pt_1, pt_2, pt_3, count, maxcount);
input Clock, Reset;
//input signed [3:0] sum;
input [3:0] pt_0, pt_1, pt_2, pt_3;
parameter signed [3:0] no_point = 4'b0000, plus_one = 4'b0001, plus_two = 4'b0010, neg_two = 4'b1110;
//input zero, negative, carry, overflow;

output signed [6:0] count, maxcount;
reg signed [6:0] count, maxcount;

////wire PS;
//reg NS;

always @(posedge Clock)
if (Reset) begin
count <= 7'b0;
maxcount <= 7'b0;
end else begin
if (count > maxcount) begin
maxcount <= count;
end
if (pt_0 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_0;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_1 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_1;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_2 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_2;
if (count > 7'b100010) begin
count <= 7'b0;
end
end

if (pt_3 == neg_two) begin
if (count < 2) begin
count <= 7'b0;
end else begin
count <= count - 2;
end
end else begin
count <= count + pt_3;
if (count > 7'b100010) begin
count <= 7'b0;
end
end
end
endmodule
Click to expand...

--

Rick
 
Perhaps you could try in comp.lang.verilog. VHDL stands for VHSIC Hardware Design Language, not Verilog Hardware Design Language. The former is typically referred to as VHDL, while the latter is sometimes referred to as Verilog HDL, or just Verilog.
 
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