Verilog Counter Glitch

[Jason Zheng]

On Sun, 24 Feb 2008 16:17:50 +0000
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote:

On Sun, 24 Feb 2008 07:45:16 -0800, Jason Zheng wrote:

Use of local variables can cause troubles too if that local variable
is assigned within the always block as the flip-flop, and that local
variable is shared by other blocks.

Was what I wrote so very unclear?

Sorry, I missed your original posting on this.

and just in case you missed it...

...BLOCKING assignment to variables
***** declared locally within the clocked process *****

Because they're declared locally, it is very unlikely that
you could mistakenly reference them from another process;
and, indeed, impossible when you come to synthesis.

I thought this is not possible, at least in Verilog 1995 style.

For Verilog bigots, the use of mixed blocking and nonblocking
assignment I described is painfully close to admitting that
VHDL got it right all along, because it is effectively the
same model that VHDL uses: variables in a process, signals
to communicate between processes.

I agree with you 100%. However, for the new-comers of Verilog, I have
to say Cliff's guidelines are much easier to follow.

~Jason Zheng
--
Nirvana? That's the place where the powers that be and their friends
hang out. -- Zonker Harris

 

[Mike Treseler]

Jason Zheng wrote:
....

If q1 is never used outside the always block, then it synthesizes to
combinational logic that feeds q2. However if q1 is ever used outside
that block, it would be turned into a flip-flop, and you end up with a
pipelined q1 and q2.

Thanks. I don't describe combinational logic, but that example
is close enough that I will concede the point and use '<=' on my port
assignments. However I will continue to use local '=' assignments
according to the the rules well described by Mr. Bromley elsewhere
in this thread to translate my single-process vhdl designs to verilog.

-- Mike Treseler

 

[Mike Treseler]

Jason Zheng wrote:

Because they're declared locally, it is very unlikely that
you could mistakenly reference them from another process;
and, indeed, impossible when you come to synthesis.

I thought this is not possible, at least in Verilog 1995 style.

1995 and 2001 works for me.

... However, for the new-comers of Verilog, I have
to say Cliff's guidelines are much easier to follow.

This thread is good evidence for that opinion.
Sorry to stir things up, but I am incurable synthesis wonk
and I find this stuff fascinating.

-- Mike Treseler