Verilog Book for VHDL Users

[rickman]

On Jan 16, 4:36 pm, Mike Treseler <mtrese...@gmail.com> wrote:

On 1/15/2011 12:09 PM, rickman wrote:

This is starting to sound like VHDL...! I don't mind being explicit.
It is just that in VHDL it can get rather confusing as to what you
need to be explicit about or how exactly to be explicit.

I find it hard to believe that there are no good texts on this.

It is true.
I found this one slightly useful:http://www.google.com/search?q=botros+isbn+1584508558

It's the only book of side by side vhdl|verilog examples in print.
But that is all it is -- simple synthesis examples and a short
explanation. No language reference or simulation examples.
But it's a quick way for a vhdl guy to get started
on verilog synthesis, and the price is right.

-- Mike Treseler

Why do you say this is the "only" text? I know of at least two others
that cover both VHDL and Verilog. One is Ben Cohen's book, "Real Chip
Design and Verification Using Verilog and VHDL". The other I have,
Douglas J. Smith, "HDL Chip Design". The Smith book has side by side
examples of both like you describe for the Botros book, but I can't
say about the Cohen book since I haven't seen it.

I will say this is the only affordable one of the three. The other
two are $167 and $135! Thats just too rich for my blood.

Rick