Using parameter from top module

I created a parameter in the top module of my code. Now I want to instantiate it to use in child modules. How can I do that?

ex.
module fifo_ddr (clk, rst, wr_en, rd_en, clk_div_wr, clk_div_rd, data, buf_full, buf_empty, write_addr, read_addr, buf_out);

parameter DATA_WIDTH=8;
parameter ADDR_WIDTH=6;

input clk, rst, wr_en, rd_en;
input[(DATA_WIDTH-1):0] data;


and then I want to use in the other module

 

[GaborSzakacs]

danilojcamara@gmail.com wrote:

I created a parameter in the top module of my code. Now I want to instantiate it to use in child modules. How can I do that?

ex.
module fifo_ddr (clk, rst, wr_en, rd_en, clk_div_wr, clk_div_rd, data, buf_full, buf_empty, write_addr, read_addr, buf_out);

parameter DATA_WIDTH=8;
parameter ADDR_WIDTH=6;

input clk, rst, wr_en, rd_en;
input[(DATA_WIDTH-1):0] data;


and then I want to use in the other module

It's easier with Verilog 2001 syntax, but you can do it the
same way you just showed. In the sub-module use the same
syntax for DATA_WIDTH and ADDR_WIDTH.

Then when you instantiate the sub-module use defparam to set
the parameters to the value from the top like:

sub_module u_sub1 (.clk (clk), .data (data), .addr (addr) . . .);

defparam u_sub1.DATA_WIDTH = DATA_WIDTH;
defparam u_sub1.ADDR_WIDTH = ADDR_WIDTH;

Or move to Verilog 2001 and it looks like:

module fifo_ddr
#(
parameter DATA_WIDTH=8,
parameter ADDR_WIDTH=6
)
(
input wire clk,
input wire reset,
input wire [DATA_WIDTH-1:0] data,
. . .
);

submodule
#(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH)
(
u_sub1
(
.clk (clk),
.rst (rst),
.data (data),
. . .
);

--
Gabor