Using Altera LPM megafunctions in Quartus II and VHDL in gen

[Shannon]

Hello all.

I've successfully used an LPM counter in my code but I can't help
feeling that I just got lucky. Something seems missing. I used the
"Megawizard thingy".

I cut and pasted the component declaration from one of the files it
created and I cut and pasted the component instantiation from one of
the files it created (editing it for my code of course). Then I added
the vhdl file it created to my project in the project window. That's
it.

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something? I'd like to say
again that everything is working fine but it just seems like something
is being assumed and when I try to move this code elsewhere its going
to break.

Shannon

 

[Mike Treseler]

Shannon wrote:

I've successfully used an LPM counter in my code but I can't help
feeling that I just got lucky. Something seems missing. I used the
"Megawizard thingy".

Portability and simplicity are missing.
On the upside, you were able to get something
working without first learning vhdl for synthesis.

I cut and pasted the component declaration from one of the files it
created and I cut and pasted the component instantiation from one of
the files it created (editing it for my code of course). Then I added
the vhdl file it created to my project in the project window. That's
it.

The alternative is to
declare a variable (or signal)
for the counter and add this
single line to your clocked process:

a_v := a_v + 1;

Then you can use the counter value a_v
for whatever you like in the rest of the
process. No components or instances required.

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something? I'd like to say
again that everything is working fine but it just seems like something
is being assumed and when I try to move this code elsewhere its going
to break.

If you don't mind the code clutter, all will be fine
until you change devices to one of the many
not made by Altera. Your lpm components are
just syntax errors to brands X, Y and Z.
This is deal you make with the wizard.

Learn synthesis or be prepared to redo
your design.

Have a look at the "clk enabled counters" example here
http://home.comcast.net/~mike_treseler/
for one way to write portable counters.

-- Mike Treseler

 

[KJ]

Mike Treseler wrote:

Your lpm components are
just syntax errors to brands X, Y and Z.
This is deal you make with the wizard.

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either, you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Kevin

 

[Mike Treseler]

KJ wrote:

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard

The lpm models were written by Altera and
were held by the now-defunct edif.org in
the public domain. The models had complex
string generics and were designed to be
fronted by a wizard application to
collect and fill in the option strings.
The files were last updated by Altera in 1999
and are now held by eia.

Xilinx has tolerated the models for synthesis
but you can find very little information
about lpm on their website.
Xilinx infers matching netlists, but
they are not named lpm.
Altera supports
the existing models, but there has not been
a new one in a long time.

it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Quartus will also infer these for you from code.


-- Mike Treseler

 

[Shannon]

On Fri, 18 Aug 2006 11:41:32 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:

KJ wrote:

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard

The lpm models were written by Altera and
were held by the now-defunct edif.org in
the public domain. The models had complex
string generics and were designed to be
fronted by a wizard application to
collect and fill in the option strings.
The files were last updated by Altera in 1999
and are now held by eia.

Xilinx has tolerated the models for synthesis
but you can find very little information
about lpm on their website.
Xilinx infers matching netlists, but
they are not named lpm.
Altera supports
the existing models, but there has not been
a new one in a long time.

it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Quartus will also infer these for you from code.


-- Mike Treseler

It seems a bit much just for a simple counter to have to write piles
of code like Mike linked to in his first response. That is why the lpm
counter seemed so simple to me. The lpm counter made the code look
nice and clean and neat and readable. Also, I assumed the lpm code
had been properly tested and vetted so that it reduces the amount of
code testing/debuging I need to do.

Harsh comments from Mike aside, what would be the "correct" way of
creating a "clean" reusable counter that includes: clock, count
enable, synchronous load, data in, and data out?

As an aside to Mike I'd like to add this:

I'm old school on the net and so my skin is pretty thick. But you
might want to conscider toning down your snide comments a bit. Act
like the person you are responding to is right in the room with you.
Maybe even act like he is a customer. I'm sure you have lots of good
things to say to help out newbies but acting like a jerk gets in the
way. I don't want to start a flame war here. My email address is
visible. I would be happy to take this offline.

Shannon

 

[David Ashley]

Shannon wrote:

As an aside to Mike I'd like to add this:

I'm old school on the net and so my skin is pretty thick. But you
might want to conscider toning down your snide comments a bit. Act
like the person you are responding to is right in the room with you.
Maybe even act like he is a customer. I'm sure you have lots of good
things to say to help out newbies but acting like a jerk gets in the
way. I don't want to start a flame war here. My email address is
visible. I would be happy to take this offline.

Shannon

Shannon,

Sorry to butt in here, I have nothing to contribute to this discussion
technically except that as a beginner myself I'm very afraid of the
wizard approach to developing solutions. It seems like if you use the
wizard you can point and click and without really having any clue
what you just did, or what is going on behind the scenes, you've got
something to work! But what have you done? And I've seen as soon
as something comes up that isn't that trivial, you have to then go to
a massive amount of effort to work *around* the wizard abstraction
to add your own VHDL code and get it integrated...my experience
comes from watching someone else fight the Xilinx tools.

Bottom line there is the wizard seems to be a crutch that maybe makes
a newby feel productive, but in the end you might be better off
without it. Just edit the raw VHDL directly and build up a library of
your own VHDL source you can draw upon. The wizards seem to
be done for marketing hype -- do professionals in the industry who
are here to stay really depend on them? I don't know, I'm not a
professional yet.

Anyway the real point of this post -- I didn't read anything in Mike's
posts in this thread that seemed harsh or snide -- was there some
posting I missed? None of my business except as a curious lurker.

-Dave

 

[KJ]

it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

Synplicity also supports LPM which, for those people who use that tool,

makes the vendor choice moot since Synplify is not tied to brand 'A' or 'X'.

you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Quartus will also infer these for you from code.

While I agree that lpm_counter (and a good chunk of lpm as well) would be
better off written more clearly simply in VHDL or Verilog than it would be
to instantate the lpm part I do not agree that things like lpm_divide and
lpm_fifo would fit into that same mold at least not at this moment in time.
Re-writing code to implement a fifo or a divider is wasted time unless done
for the learning experience in which case it may be time well spent.

It seems a bit much just for a simple counter to have to write piles
of code like Mike linked to in his first response. That is why the lpm
counter seemed so simple to me. The lpm counter made the code look
nice and clean and neat and readable.

And that is pretty much the deciding factor....what makes the code "look
nice and clean and neat and readable" which I think would translate into
"more readily supportable" which should be a goal (albeit hard to measure)
of anyone writing code.

Mike's point (with which I agree) is that for the case of a counter in a
real design it will be much more understandable to simply write 'x := x + 1'
then it would be to instantiate lpm_counter.

Also, I assumed the lpm code
had been properly tested and vetted so that it reduces the amount of
code testing/debuging I need to do.

Yes it has. If the tool supports it (and several do support lpm) than

you're correct.

KJ

 

[Ben Twijnstra]

Shannon wrote:

Harsh comments from Mike aside, what would be the "correct" way of
creating a "clean" reusable counter that includes: clock, count
enable, synchronous load, data in, and data out?

Counters are easily written - like some other posters already said, just
declare a signal, and, when appropriate say something like

-- At the top of your file say
library ieee;
use ieee.std_logic_1164.all;
use ieee.num_std.all;

-- somewhere in the architecture declaration area, say
signal data_out : unsigned(0 to 999);
-- assume data_in to be an unsigned(0 to 999) on the entity port list
-- assume clock, count_enable and sync_load to be std_logic
....
-- Now, somewhere in the actual architecture body say

instance_name: process(clock, count_enable, data_in)
begin
if rising_edge(clock) then
if sync_load = '1' then
data_out <= data_in;
elsif count_enable = '1' then
data_out <= data_out + 1;
end if;
end if;
end process;

See how easy this is?

Now, with division, things are a lot more difficult. Especially if I can't
think my way out of using a divider, I'll allways use a wizard-generated
divider - greater minds than mine have sweated over the efficient
algorithms that are used in those beasts. For a multiplier I simply use
the '*' operator - life can be so simple...

Best regards,


Ben

 

[Mark McDougall]

Shannon wrote:

I cut and pasted the component declaration from one of the files it
created and I cut and pasted the component instantiation from one of
the files it created (editing it for my code of course). Then I added
the vhdl file it created to my project in the project window. That's
it.

I think everyone in this thread has gone out on a tangent and he
responses have nothing to do with the question Shannon actually asked!?!

The point is not whether or not using the LPM is portable or even the
best solution for a counter (clearly it's not) but whether or not
Shannon is using the LPM component correctly.

In short Shannon, yes, that's exactly what you need to do. The
megawizard "thingy" merely assists in parameterising the component with
a point-and-click interface. You could of course achieve exactly the
same in pure VHDL yourself - you'd end up with the component declaration
and the VHDL file you included from the megawizard output.

Naturally you also need to instantiate your component, hence the second
step you took. The third step, adding the VHDL file, just imports the
(thin) wrapper that the megawizard created with all your parameters for
that particular instance.

As for including libraries etc, you notice the wrapper VHDL file you
included uses the altera_mf_components library.

Regards

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[KJ]

"Mark McDougall" <markm@vl.com.au> wrote in message
news:44e90499$0$4137$5a62ac22@per-qv1-newsreader-01.iinet.net.au...

I think everyone in this thread has gone out on a tangent and he
responses have nothing to do with the question Shannon actually asked!?!

Well, to be fair there were some implicit questions in the original post
regarding portability of the code that has been produced. But I see you've
continued the tradition of going off on a tangent by yourself not answering
the one single question that was in the original post (pasted below for
those that forgot)

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something?

The answer: No the library use clause is not needed if you use direct
instantiation (i.e.something of the form U1 : entity work.MyComponent port
map(...);

KJ

 

[Andy]

Mike's example, while very well put together, is functionally more
complex than what you require (it does more, not just takes more
typing). Your requirements can be met with code as simple as:

process (clk) is
variable data : unsigned(data_out'range);
begin
if rising_edge(clk) then
if synchronous_reset = '1' then
data := (others => '0');
elsif synchronous_load = '1' then
data := data_in;
elsif count_enable = '1' then
data := data + 1;
end if;
end if;
data_out <= data; -- copy data to data_out
end process;

Assumptions:
1. data_out is a port of mode out that cannot be read.
2. data_out and data_in are both of type numeric_std.unsigned.
3. data_out and data_in are the same size.

Note that you did not specify a reset, but I added a synchronous one.
Adding an async reset would be just as trivial.

You could always encapsulate the above process in an
entity/architecture, but then it would be necessary to generate the
control inputs for it. Sometimes it is easier and more self documenting
to just merge a counter function into a state machine than it is to
generate the signals to communicate with a separate counter. Especially
when you want things done on the same clock edge (i.e. no register
delays).

LPM fifos and memories can only store std_logic_vector data types. What
happens when you want to store enumerated types, arrays, and/or
records? If you know how to infer memories and counters, fifos are
easily designed of any size and any content type you want.

Andy


Shannon wrote:

On Fri, 18 Aug 2006 11:41:32 -0700, Mike Treseler
mike_treseler@comcast.net> wrote:

KJ wrote:

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard

The lpm models were written by Altera and
were held by the now-defunct edif.org in
the public domain. The models had complex
string generics and were designed to be
fronted by a wizard application to
collect and fill in the option strings.
The files were last updated by Altera in 1999
and are now held by eia.

Xilinx has tolerated the models for synthesis
but you can find very little information
about lpm on their website.
Xilinx infers matching netlists, but
they are not named lpm.
Altera supports
the existing models, but there has not been
a new one in a long time.

it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Quartus will also infer these for you from code.


-- Mike Treseler

It seems a bit much just for a simple counter to have to write piles
of code like Mike linked to in his first response. That is why the lpm
counter seemed so simple to me. The lpm counter made the code look
nice and clean and neat and readable. Also, I assumed the lpm code
had been properly tested and vetted so that it reduces the amount of
code testing/debuging I need to do.

Harsh comments from Mike aside, what would be the "correct" way of
creating a "clean" reusable counter that includes: clock, count
enable, synchronous load, data in, and data out?

As an aside to Mike I'd like to add this:

I'm old school on the net and so my skin is pretty thick. But you
might want to conscider toning down your snide comments a bit. Act
like the person you are responding to is right in the room with you.
Maybe even act like he is a customer. I'm sure you have lots of good
things to say to help out newbies but acting like a jerk gets in the
way. I don't want to start a flame war here. My email address is
visible. I would be happy to take this offline.

Shannon

 

[Mark McDougall]

KJ wrote:

But I see you've
continued the tradition of going off on a tangent by yourself not answering
the one single question that was in the original post (pasted below for
those that forgot)

I'm going to assume that English is not your native language because my
response directly addresses the concerns the OP had in *all* but the
very last sentence. Just because the preceding sentences weren't
terminated with a question mark doesn't mean the OP wasn't looking for
some sort of re-assurance.

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something?
The answer: No the library use clause is not needed if you use direct
instantiation (i.e.something of the form U1 : entity work.MyComponent port
map(...);

So you've ignored the gist of the post altogether and instead given a
totally irrelevant 'answer' to the final question.

The actual point is that the VHDL wrapper created by the megafunction
wizard uses the appropriate library, which is why the instantiating
module doesn't need to know about megafunctions.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[KJ]

"Mark McDougall" <markm@vl.com.au> wrote in message
news:44eba306$0$4162$5a62ac22@per-qv1-newsreader-01.iinet.net.au...

KJ wrote:

But I see you've
continued the tradition of going off on a tangent by yourself not
answering
the one single question that was in the original post (pasted below for
those that forgot)

I'm going to assume that English is not your native language because my
response directly addresses the concerns the OP had in

My English is just fine thank you....I even have the ability to type
'original post' instead of 'OP'. Since the original post was quite
civilized and you've chosen personal insults in your reply that this would
seem to be another one of those 'thread tangents' that you were mentioning.
In this case, I agree that this particular tangent should be shut down.

*all* but the very last sentence.

You mean the sentence that actually ended with the question mark...which
really was a question....the one I answered.

I agree that this particular question was not the poster's main point (which
had been addressed) I just found it funny that your reply said that the
thread had not answered the poster's question and when I looked back there
was only one sentence actually ending in a question mark and indeed it had
not been answered in the thread....or by you...even after making that
statement. So I humorously (but accurately) answered that one last
question.

Just because the preceding sentences weren't
terminated with a question mark doesn't mean the OP wasn't looking for
some sort of re-assurance.

That's your interpretation that the original poster wanted re-assurance.

It seemed to me more of a question of 'Is using the wizard a good design
practice?', 'What are the pros and cons about getting help from Mr.
Wizard?', 'What happens if I target my design to some other device?', that
type of thing was my interpretation. While I won't speak for them, given
the earlier posts from Mike, David, Ben and Andy it would appear to me that
they were probably interpreting it that way too.

I feel like I'm getting away with this but it's not rigorous.
Shouldn't I need a library use clause or something?
The answer: No the library use clause is not needed if you use direct
instantiation (i.e.something of the form U1 : entity work.MyComponent
port
map(...);

So you've ignored the gist of the post altogether and instead given a
totally irrelevant 'answer' to the final question.

No, the 'gist of the post' I think had been adequately addressed already by
the earlier posts (in fact, most of it was covered by Mike's first post in
my opinion). You stated that "everyone in this thread has gone out on a
tangent and the responses have nothing to do with the question" and then you
went off on your own tangent based on your interpretation of what the poster
was looking for. I would suggest that you could have simply replied with
your post without insulting the earlier posters with your "everone in this
thread..." commentary.

The actual point is that the VHDL wrapper created by the megafunction
wizard uses the appropriate library, which is why the instantiating
module doesn't need to know about megafunctions.

Not at all. The fact that the wizard created a wrapper only changes the
name of the entity that will get instantiated by the instantiating module,
it doesn't remove or add any 'library' or 'use' statements (if one chooses
not to use direct instantiation). While it's true that the instantiating
module would not need to know about the function that had been wrapped (in
this case entity 'lpm_counter') but it would need to know about the wrapped
entity (i.e. 'My_MegaWizard_Counter'). Either way, you need to know the
name of an entity and where to find it.

KJ

 

[Shannon]

WOW!!!! Ok, Fantastic answers! You guys are awesome! This was the
kind of answers I was looking for. And thank you Mark McDougall for
answering my specific questions. And thank the rest of you for
extending the discussion beyond my basic questions.

I am a newbie to VHDL but I've been a hardware engineer for almost 10
years. In those 10 years I've done a LOT of PLD coding in PALASM..yes
PALASM and quite a bit of coding in AHDL. I've decided to make the
move recently to VHDL to improve my formalism a bit. I'm still a
hardware guy for the most part. About 20% of my job is VHDL.

So, one last question. Is the LPM counter function (I'm talking about
the Altera brand here) a sychronous counter or a ripple counter? From
my basic understanding the examples like the one below from Andy would
result in a ripple counter.

Thanks again,
Shannon

On 22 Aug 2006 15:46:00 -0700, "Andy" <jonesandy@comcast.net> wrote:

Mike's example, while very well put together, is functionally more
complex than what you require (it does more, not just takes more
typing). Your requirements can be met with code as simple as:

process (clk) is
variable data : unsigned(data_out'range);
begin
if rising_edge(clk) then
if synchronous_reset = '1' then
data := (others => '0');
elsif synchronous_load = '1' then
data := data_in;
elsif count_enable = '1' then
data := data + 1;
end if;
end if;
data_out <= data; -- copy data to data_out
end process;

Assumptions:
1. data_out is a port of mode out that cannot be read.
2. data_out and data_in are both of type numeric_std.unsigned.
3. data_out and data_in are the same size.

Note that you did not specify a reset, but I added a synchronous one.
Adding an async reset would be just as trivial.

You could always encapsulate the above process in an
entity/architecture, but then it would be necessary to generate the
control inputs for it. Sometimes it is easier and more self documenting
to just merge a counter function into a state machine than it is to
generate the signals to communicate with a separate counter. Especially
when you want things done on the same clock edge (i.e. no register
delays).

LPM fifos and memories can only store std_logic_vector data types. What
happens when you want to store enumerated types, arrays, and/or
records? If you know how to infer memories and counters, fifos are
easily designed of any size and any content type you want.

Andy


Shannon wrote:
On Fri, 18 Aug 2006 11:41:32 -0700, Mike Treseler
mike_treseler@comcast.net> wrote:

KJ wrote:

Actually 'LPM' (Library of parameterizable modules) is fairly portable
and is (I think) an EIA standard

The lpm models were written by Altera and
were held by the now-defunct edif.org in
the public domain. The models had complex
string generics and were designed to be
fronted by a wizard application to
collect and fill in the option strings.
The files were last updated by Altera in 1999
and are now held by eia.

Xilinx has tolerated the models for synthesis
but you can find very little information
about lpm on their website.
Xilinx infers matching netlists, but
they are not named lpm.
Altera supports
the existing models, but there has not been
a new one in a long time.

it's the MegaWizard produced files
that are not and are specific to company 'A'. Within LPM, besides the
stupid things like 'and', 'or', etc. there are some useful ones like
'lpm_divide', 'lpm_ram', 'lpm_rom', 'lpm_fifo' (and variants on those).
But you don't need a wizard to use these parts either,

True for Altera. Tough otherwise since the source
code is no longer public.

you simply
instantiate the lpm component hooking up signals, defining the
generics, etc just like you would any other entity.

Quartus will also infer these for you from code.


-- Mike Treseler

It seems a bit much just for a simple counter to have to write piles
of code like Mike linked to in his first response. That is why the lpm
counter seemed so simple to me. The lpm counter made the code look
nice and clean and neat and readable. Also, I assumed the lpm code
had been properly tested and vetted so that it reduces the amount of
code testing/debuging I need to do.

Harsh comments from Mike aside, what would be the "correct" way of
creating a "clean" reusable counter that includes: clock, count
enable, synchronous load, data in, and data out?

As an aside to Mike I'd like to add this:

I'm old school on the net and so my skin is pretty thick. But you
might want to conscider toning down your snide comments a bit. Act
like the person you are responding to is right in the room with you.
Maybe even act like he is a customer. I'm sure you have lots of good
things to say to help out newbies but acting like a jerk gets in the
way. I don't want to start a flame war here. My email address is
visible. I would be happy to take this offline.

Shannon

 

[Shannon]

Oh I forgot one last thing. What do people think of the book:

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability,
and Scalability by Pong P. Chu.

I was thinking of adding that one to my new collection:

The Designer's Guide to VHDL, Second Edition By: Peter J. Ashenden
VHDL for Logic Synthesis By: Andrew Rushton
Circuit Design with VHDL By: Volnei A. Pedroni
A VHDL Synthesis Primer, Second Edition By: Jayaram Bhasker

 

[KJ]

Shannon wrote:

So, one last question. Is the LPM counter function (I'm talking about
the Altera brand here) a sychronous counter or a ripple counter? From
my basic understanding the examples like the one below from Andy would
result in a ripple counter.

lpm_counter and Andy's counter are both synchronous counters not ripple
counters.

KJ

 

[David Ashley]

Shannon wrote:

Oh I forgot one last thing. What do people think of the book:

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability,
and Scalability by Pong P. Chu.

I was thinking of adding that one to my new collection:

The Designer's Guide to VHDL, Second Edition By: Peter J. Ashenden
VHDL for Logic Synthesis By: Andrew Rushton
Circuit Design with VHDL By: Volnei A. Pedroni
A VHDL Synthesis Primer, Second Edition By: Jayaram Bhasker

Shannon,

I only have one book on VHDL, it's the Ashendon one. I think
one is enough, you need to stop studying and get your hands dirty
coding. Meaning the knowledge from any of your books has to be
in your head, not your library :^).

The internet's a better resource anyway.

Having said all that your new book sounds very interesting.
Maybe I'll buy a copy.

-Dave

 

[KJ]

I have and can recommend

VHDL for Logic Synthesis By: Andrew Rushton

I haven't perused the others so I don't know how they compare

KJ

 

[Andy]

Since you mentioned AHDL, Xilinx has an AHDL to VHDL translator, but
the license restrictions placed on the output VHDL source file restrict
its use to Xilinx hardware. Oddly enough, Altera, the owner of AHDL,
does not provide a translator from AHDL to VHDL.

The produced code is not too bad to look at to see at least a
rudimentary example of synthesizable VHDL. Of course a lot of AHDL has
been written targetting PLDs that do not have the same design
restrictions (mostly regarding clock distribution, and the extreme
desire to not use more clock signals than you absolutely have to), so
porting that code to VHDL and targeting an FPGA does not ensure
success.

As to texts on VHDL, don't limit yourself to "standard, synthesizable
VHDL" for your coding, especially when coding testbenches for your FPGA
designs. VHDL is a much more powerful language than would otherwise be
indicated by the tiny fraction of it actually used by most designers.
Experiment with coding styles to see what works well for you, even in
synthesizable code. Try coding up common functions and then using your
synthesis tool's schematic level viewer to see what you got.

Andy

 

[Mark McDougall]

KJ wrote:

Since the original post was quite
civilized and you've chosen personal insults in your reply that this would
seem to be another one of those 'thread tangents' that you were mentioning.
(snip)
So I humorously (but accurately) answered that one last
question.

You caught me in a particularly bad mood yesterday morning and I failed
to see the "humour" in your response - rather your post came across as a
swipe at me. I thought I'd carefully tempered my response to be no more
or less "insulting" than yours - obviously you didn't see it that way.
For that I apologize.

In any case, I think I've been vindicated with the original poster's
response elsewhere in this thread.

End of tangent!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266