Use of libraries

[NigelE]

On Jul 23, 12:08 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:

"Martin Thompson" <martin.j.thomp...@trw.com> wrote in message

news:uzm1nsbcb.fsf@trw.com...>> This is with Modelsim and I typically do a
'Compile out of date' from the GUI and go right on back to simulating.

That's a feature of Modelsim I didn't know about - thanks! I shall
have to find out how to do this from the vsim command-line ;-) I hate
mices...

I looked a little bit for a command line way to do it without luck so if you
do find such a command post it back up here.

KJ

The "Compile Out Of Date" relies on you using the ModelSim project
capability and requires a <project>.mpf file which references the
source files, libraries and compile & simulation commands.
Projects are most usually/easily managed via the GUI but the 'project'
command includes the compileoutofdate option.

cheers

- Nigel

This funct

 

[KJ]

On Jul 23, 8:43 am, NigelE <nigel_ell...@mentor.com> wrote:

On Jul 23, 12:08 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:

"Martin Thompson" <martin.j.thomp...@trw.com> wrote in message

news:uzm1nsbcb.fsf@trw.com...>> This is with Modelsim and I typically do a
'Compile out of date' from the GUI and go right on back to simulating.

That's a feature of Modelsim I didn't know about - thanks! I shall
have to find out how to do this from the vsim command-line ;-) I hate
mices...

I looked a little bit for a command line way to do it without luck so if you
do find such a command post it back up here.

KJ

the 'project'
command includes the compileoutofdate option.

Thanks.

KJ

 

[Mike Treseler]

NigelE wrote:

vcom -just p *.vhd
vcom -just b *.vhd
vcom -just e *.vhd
vcom -just a *.vhd
vcom -just c *.vhd

is a generic compile script that should compile your files in the
correct order, independent of how you've organised your design units.

That is a good first try, if I lack a makefile,
but overlapping/duplicate declarations can make this fail.

-- Mike Treseler

 

[Mike Treseler]

Martin Thompson wrote:

I shall have to consider that, although getting my Emacs fingers out
of the habit of prodding C-sC-cC-k then ALT-TAB, up-arrow ENTER to
compile and sim will be hard

Or, maybe stick with vhdl-make.
It can be worth the wait.

If I forget about some package edit
I made at the beginning of my session,
'Compile out of date' may lead me
on a long debug session.

Also, the GUI project manager has
its own annoyances and is a weak
substitute for vhdl-mode projects.

I have found it impossible to keep
both modelsim.ini and .mpf managers
in synch. So one or the other
is probably better than both.

-- Mike Treseler

 

[KJ]

On Jul 23, 1:21 pm, Mike Treseler <mike_trese...@comcast.net> wrote:

Martin Thompson wrote:
I shall have to consider that, although getting my Emacs fingers out
of the habit of prodding C-sC-cC-k then ALT-TAB, up-arrow ENTER to
compile and sim will be hard

Or, maybe stick with vhdl-make.
It can be worth the wait.
Hey....I thought earlier in the thread you implied (at least to me)

that this was lightning quick

If I forget about some package edit
I made at the beginning of my session,
'Compile out of date' may lead me
on a long debug session.

For what it's worth, I haven't found that to be the case. If

something changes inside a package/entity that will require a re-
compile of some dependent file that was not changed (and therefore not
caught by 'Compile out of date' then it gets flagged as soon as you
vsim. The message is pretty clear, telling you which design unit
needs to be recompiled because package 'xyz' has been changed.

The amount of lost time would be the time spent loading the design up
to the point of the failure (which I'm guessing for most would be less
than 1 minute), not any debug time (since you can't get that far). In
any case, you would recompile the dependent files and get back to
siming.

This is all on the assumption that the file dependencies have all been
worked out correctly to begin with....and if they haven't....well, the
GUI (and I'm guessing the command line too based on NigelE's earlier
post) does have a 'generate compile order' option as well. Whether
that is better or worse than what people use to generate file
dependency orders to feed into make is something for each to decide.

Kevin Jennings

 

[Mike Treseler]

KJ wrote:

Hey....I thought earlier in the thread you implied (at least to me)
that this was lightning quick

Yes. I guess Martin's mileage varied

The amount of lost time would be the time spent loading the design up
to the point of the failure

.... and probably much less time than I've
spent piffling about it on usenet.

Thanks for the comments.
Back to the salt mines.

-- Mike Treseler

 

[Paul Uiterlinden]

Mike Treseler wrote:

NigelE wrote:

vcom -just p *.vhd
vcom -just b *.vhd
vcom -just e *.vhd
vcom -just a *.vhd
vcom -just c *.vhd

is a generic compile script that should compile your files in the
correct order, independent of how you've organised your design units.


That is a good first try, if I lack a makefile,
but overlapping/duplicate declarations can make this fail.

As do use clauses of packages in packages.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

 

[jtw]

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:5g803eF3ffa9mU1@mid.individual.net...

KJ wrote:

As in your example, package, entity and architecture in the same file is
also typically what I do in most circumstances.

My point was that if you though you could avoid name clashing by
compiling the file stack.vhd to the 'mikes_stack_lib' library then you
would need to replace references such as
work.stack_pkg.whatever
with
mikes_stack_lib.stack_pkg.whatever

I was advocating compiling everything into work
and Peter wanted separate libraries, but that's right.
If I did compile into 'mikes_stack_lib' then I either
have to map that name to 'work' -- if that is possible --

It is, indeed, possible, at least with Modelsim. Synplicity's project
files depend a little less on library names.

JTW

or edit the code.

-- Mike Treseler

 

[Martin Thompson]

Mike Treseler <mike_treseler@comcast.net> writes:

KJ wrote:


Hey....I thought earlier in the thread you implied (at least to me)
that this was lightning quick

Yes. I guess Martin's mileage varied

But I now have the best of both worlds!

Reading the Modelsim docs ("engineer in 'reads documentation'
shock!"), it appears the command line vcom is clever enough to only
update the bits of the library that need it, so if you only change the
architecture in a file, it only compiles the architecture. So you can
put all your stuff in one file and use the Emacs Compile-File with
impunity. On the occasions you need to compile lots of stuff,
the makefile is still there as well. Yay - I like finding new stuff
out!

From the docs:

"vcom determines whether or not the compilation results have
changed. For example, if you keep an entity and its architectures in
the same source file and you modify only an architecture and recompile
the source file, the entity compilation results will remain unchanged
and you will not have to recompile design units that depend on the
entity."

Which probably says it better than I did

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[Martin Thompson]

Paul Uiterlinden <puiterl@notaimvalley.nl> writes:

Mike Treseler wrote:

NigelE wrote:

vcom -just p *.vhd
vcom -just b *.vhd
vcom -just e *.vhd
vcom -just a *.vhd
vcom -just c *.vhd

is a generic compile script that should compile your files in the
correct order, independent of how you've organised your design units.


That is a good first try, if I lack a makefile,
but overlapping/duplicate declarations can make this fail.

As do use clauses of packages in packages.

I have a script which iterates over all my files compiling packages
until there are no errors, then I do the entities, and then I do all
the rest. Then I can use vmake to make a Makefile. I've given up on
VHDL-mode's makefile creator - I'm a heavy user of folding-mode, and
having lots of buffers open at once. VHDL-mode doesn't see inside any
closed folds of open files, so when I regenerate a makefile I have to
close all my buffers first :-(

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[Martin Thompson]

"KJ" <kkjennings@sbcglobal.net> writes:

"Martin Thompson" <martin.j.thompson@trw.com> wrote in message
news:uzm1nsbcb.fsf@trw.com...
This is with Modelsim and I typically do a
'Compile out of date' from the GUI and go right on back to simulating.

That's a feature of Modelsim I didn't know about - thanks! I shall
have to find out how to do this from the vsim command-line ;-) I hate
mices...

I looked a little bit for a command line way to do it without luck so if you
do find such a command post it back up here.

See upthread, if you haven't already, vcom does it by magic already!

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[Mike Treseler]

Martin Thompson wrote:

I have a script which iterates over all my files compiling packages
until there are no errors, then I do the entities, and then I do all
the rest. Then I can use vmake to make a Makefile. I've given up on
VHDL-mode's makefile creator - I'm a heavy user of folding-mode, and
having lots of buffers open at once. VHDL-mode doesn't see inside any
closed folds of open files, so when I regenerate a makefile I have to
close all my buffers first :-(

Check out rescan-project on the speedbar.
Then generate-makefile.

-- Mike Treseler

 

[Martin Thompson]

Mike Treseler <mike_treseler@comcast.net> writes:

Martin Thompson wrote:

I have a script which iterates over all my files compiling packages
until there are no errors, then I do the entities, and then I do all
the rest. Then I can use vmake to make a Makefile. I've given up on
VHDL-mode's makefile creator - I'm a heavy user of folding-mode, and
having lots of buffers open at once. VHDL-mode doesn't see inside any
closed folds of open files, so when I regenerate a makefile I have to
close all my buffers first :-(

Check out rescan-project on the speedbar.
Then generate-makefile.

I have never had much success with rescanning unless I go through all
the open buffers making sure they have their folds unfolded, otherwise
rescan misses dependencies.

As an aside - I also never found out out to do a rescan from the
keyboard.. I hate the pointy-clicky thing

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html