unsigned(), unsigned'(), to_unsigned()

[Shannon]

Ok, I struggle with this each and every time. Can someone help
clarify for me when each version of these is valid to use? They all
look so similar to me but I have to randomly guess each time I want to
use one type of signal with a different type of signal.

TIA,
Shannon

 

[Tim McBrayer]

Shannon wrote:

Ok, I struggle with this each and every time. Can someone help
clarify for me when each version of these is valid to use? They all
look so similar to me but I have to randomly guess each time I want to
use one type of signal with a different type of signal.

I'll give it a shot. I am assuming here that you are using either IEEE.NUMERIC_BIT or
IEEE.NUMERIC_STD for the definition of signed/unsigned.

unsigned(<expr&gt is a type conversion, and part of the base language. A type conversion
provides for explicit conversion between closely related types. Without considering
user-defined types, <expr> will be one of: std_logic_vector, std_ulogic_vector, or signed.

unsigned'(<expr&gt is a qualified expression, and also part of the base language. It is
used to explicitly provide the type and/or subtype of an expression. This is common when
the type of <expr> is not known from the context, as perhaps with a bit string literal.
This is less commonly needed than a type conversion, as VHDL is usually pretty good at
figuring out from the context what e.g. the type of "00001111" needs to be.

to_unsigned(<expr>, <size&gt is a function in IEEE.NUMERIC_[STD|BIT] that accepts an <expr>
of type NATURAL (a non-negative integer) and converts it to a unsigned vector of length
<size>.

Regards,
--
Tim McBrayer
x4229

 

[Mike Treseler]

Tim McBrayer wrote:

Shannon wrote: Re: unsigned(), unsigned'(), to_unsigned()
Ok, I struggle with this each and every time. Can someone help
clarify for me when each version of these is valid to use?

If I declare my numeric registers as unsigned, signed or integer range,
I don't need any of them.

-- Mike Treseler

 

[Jim Lewis]

Mike

If I declare my numeric registers as unsigned, signed or integer range,
I don't need any of them.

-- Mike Treseler

Do you make your external data bus unsigned? It may carry
some untyped stuff and some unsigned as well.

I have been in the habit of making all top level signals
as std_logic_vector - hopefully just a historical thing that
was due to older ASIC synthesis tools strongly preferred
std_logic_vector over any other type at the top level).

As a result, I use type conversions when loading the
std_logic_vector data bus into my unsigned programmable timers.

Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.

 

[Mike Treseler]

Jim Lewis wrote:

Mike
If I declare my numeric registers as unsigned, signed or integer range,
I don't need any of them.

-- Mike Treseler

Do you make your external data bus unsigned?

Not for device pins.
For everything else it's up to the designer.

I have been in the habit of making all top level signals
as std_logic_vector - hopefully just a historical thing that
was due to older ASIC synthesis tools strongly preferred
std_logic_vector over any other type at the top level).
As a result, I use type conversions when loading the
std_logic_vector data bus into my unsigned programmable timers.

If I use one of your modules,
I guess I will have to use conversions as well

-- Mike Treseler

 

[Shannon]

On Feb 13, 10:05 am, Jim Lewis <j...@synthworks.com> wrote:

Mike

If I declare my numeric registers as unsigned, signed or integer range,
I don't need any of them.

      -- Mike Treseler

Do you make your external data bus unsigned?  It may carry
some untyped stuff and some unsigned as well.

I have been in the habit of making all top level signals
as std_logic_vector - hopefully just a historical thing that
was due to older ASIC synthesis tools strongly preferred
std_logic_vector over any other type at the top level).

As a result, I use type conversions when loading the
std_logic_vector data bus into my unsigned programmable timers.

Jim
--

Exactly my situation as well. Thank you for the help. I know I will
still run into confusion on this problem. I've posted here many times
when the synthesis tool can't figure out what type to choose for
something ambiguous.

Shannon

 

[Brian Drummond]

On Fri, 13 Feb 2009 10:05:11 -0800, Jim Lewis <jim@synthworks.com> wrote:

Mike
If I declare my numeric registers as unsigned, signed or integer range,
I don't need any of them.

-- Mike Treseler

Do you make your external data bus unsigned? It may carry
some untyped stuff and some unsigned as well.

I have been in the habit of making all top level signals
as std_logic_vector - hopefully just a historical thing that
was due to older ASIC synthesis tools strongly preferred
std_logic_vector over any other type at the top level).

Only needed in FPGA tools now at the very top level - the I/O pins of a chip.
Even there, you can synthesise unsigned; but if you need to switch between RTL
and post-synth netlist versions in your testbench, you'd better use
std_logic_vector, because the netlist won't preserve numeric_std ports.

- Brian