triggered and oscillate a clock

[sdguy]

Hi all,

I am implementing vernier interpolation principles and I am trying to
to triggered a clock by a start signal.

Input: ref_clk 100mhz
Input: start
Output: start_clk 95 mhz

I can generate the two clocks with DCM using a virtex 4 but I don't
want the start_clk to run right away when the program powered up. I
want the input start when goes high, to trigger start_clk to
oscillate. Someone suggested using BUFGCE with start as CE. but
BUFGCE take a running clock and output when CE goes high. I want
input start to actually start the oscillation when start goes high.
does anyone have a suggestion? thanks

 

On 15 Apr., 01:53, sdguy <tringuyen...@gmail.com> wrote:

Hi all,

I am implementing vernier interpolation principles and I am trying to
to triggered a clock by a start signal.

Input: ref_clk 100mhz
Input: start
Output: start_clk 95 mhz

I can generate the two clocks with DCM using a virtex 4 but I don't
want the start_clk to run right away when the program powered up.  I
want the input start when goes high, to trigger start_clk to
oscillate.  Someone suggested using BUFGCE with start as CE.  but
BUFGCE take a running clock and output when CE goes high.  I want
input start to actually start the oscillation when start goes high.
does anyone have a suggestion?  thanks

Hi sdguy,
first of all: you can't power up a program. Programms are lists off
commands for processors (ore more generic: programmable automatons).
These are build in hardware which requres power to work. So you can
only power up hardware.

Now to your problem. Why would you want to power up a oscillator or
DCM later than the rest of your Hardware? Is it for power saving
purposes? Well, ok then. But keep in mind the physics. Both circuits
need some time to stabilize after power up. DCMs have the LOCKED
output to tell you when the clock outputs are stable. So there will be
a considerable, but hardly determinable delay between your start
signal and the availability of a stable clock. Can you deal with that
in your design?

To me the BUFGCE idea sounds quite good, even when power saving is
required.
I guess that the power used by the running DCM alone (that is just
driving the net to the BUFGCE-Input) is just a fraction of the power
consumtion of the driven clock net when your design gets the start
signal.
You may make some power measurements on a test circuit to verify my
assumption.

So, what other reasons do you have for your strange requirement?
Have a nice synthesis
Eilert

 

[sdguy]

On Apr 15, 11:13 pm, goo...@twinmail.de wrote:

On 15 Apr., 01:53, sdguy <tringuyen...@gmail.com> wrote:



Hi all,

I am implementing vernier interpolation principles and I am trying to
to triggered a clock by a start signal.

Input: ref_clk 100mhz
Input: start
Output: start_clk 95 mhz

I can generate the two clocks with DCM using a virtex 4 but I don't
want the start_clk to run right away when the program powered up.  I
want the input start when goes high, to trigger start_clk to
oscillate.  Someone suggested using BUFGCE with start as CE.  but
BUFGCE take a running clock and output when CE goes high.  I want
input start to actually start the oscillation when start goes high.
does anyone have a suggestion?  thanks

Hi sdguy,
first of all: you can't power up a program. Programms are lists off
commands for processors (ore more generic: programmable automatons).
These are build in hardware which requres power to work. So you can
only power up hardware.

Now to your problem. Why would you want to power up a oscillator or
DCM later than the rest of your Hardware? Is it for power saving
purposes? Well, ok then. But keep in mind the physics. Both circuits
need some time to stabilize after power up. DCMs have the LOCKED
output to tell you when the clock outputs are stable. So there will be
a considerable, but hardly determinable delay between your start
signal and the availability of a stable clock. Can you deal with that
in your design?

To me the BUFGCE idea sounds quite good, even when power saving is
required.
I guess that the power used by the running DCM alone (that is just
driving the net to the BUFGCE-Input) is just a fraction of the power
consumtion of the driven clock net when your design gets the start
signal.
You may make some power measurements on a test circuit to verify my
assumption.

So, what other reasons do you have for your strange requirement?
Have a nice synthesis
  Eilert

Hi Eilert,

what I am trying to do is much better describe in this google book
links below (synchronization of digital network). It required that
start trigger a clock. It has nothing to do with power saving.

books.google.com/books?isbn=0471615501 and go to page 326

thanks

 

On 16 Apr., 08:53, sdguy <tringuyen...@gmail.com> wrote:

On Apr 15, 11:13 pm, goo...@twinmail.de wrote:



On 15 Apr., 01:53, sdguy <tringuyen...@gmail.com> wrote:

Hi all,

I am implementing vernier interpolation principles and I am trying to
to triggered a clock by a start signal.

Input: ref_clk 100mhz
Input: start
Output: start_clk 95 mhz

I can generate the two clocks with DCM using a virtex 4 but I don't
want the start_clk to run right away when the program powered up.  I
want the input start when goes high, to trigger start_clk to
oscillate.  Someone suggested using BUFGCE with start as CE.  but
BUFGCE take a running clock and output when CE goes high.  I want
input start to actually start the oscillation when start goes high.
does anyone have a suggestion?  thanks

Hi sdguy,
first of all: you can't power up a program. Programms are lists off
commands for processors (ore more generic: programmable automatons).
These are build in hardware which requres power to work. So you can
only power up hardware.

Now to your problem. Why would you want to power up a oscillator or
DCM later than the rest of your Hardware? Is it for power saving
purposes? Well, ok then. But keep in mind the physics. Both circuits
need some time to stabilize after power up. DCMs have the LOCKED
output to tell you when the clock outputs are stable. So there will be
a considerable, but hardly determinable delay between your start
signal and the availability of a stable clock. Can you deal with that
in your design?

To me the BUFGCE idea sounds quite good, even when power saving is
required.
I guess that the power used by the running DCM alone (that is just
driving the net to the BUFGCE-Input) is just a fraction of the power
consumtion of the driven clock net when your design gets the start
signal.
You may make some power measurements on a test circuit to verify my
assumption.

So, what other reasons do you have for your strange requirement?
Have a nice synthesis
  Eilert

Hi Eilert,

what I am trying to do is much better describe in this google book
links below (synchronization of digital network).  It required that
start trigger a clock.  It has nothing to do with power saving.

books.google.com/books?isbn=0471615501  and go to page 326

thanks

Hi sdguy,
ok, you are going to create a digital nonius.
Nice application. But if you are trying to create a "textbook
solution", like shown in the pictures on page 326 you are about to
fail.

Things to consider here:
The input events for start and stop of the two deviant clocks are
asynchronous.
There's probably no solution to synchronize a stable clock to an
asynchronous event as required.
But: You may synchronize your event to the deviant clock (simple 2
stage shift register)

In this case you get a measurement error due to the synchronization.
Find out if that error is acceptable for your application or not.

The good news is:
With such a simple design you don't have to hassle around with BUFGCEs
and so on. The events will just trigger some FSM and/or counters
running on the deviant clocks.

The bad news is:
You have to determine when the reference clock and the deviant clock
are switching at the same time.
Tricky thing, because your clocks are probably 50% duty cycle clocks,
while the book works with discrete events (like delta impulses).
How nice it looks in theory, but its a PITA when you want to build
some real hardware.
Because a delda impulse is just a theoretical construct. You can
approcimate it by creating clocks with a very low duty cycle.
Still you will get some measurement error due to this fact which needs
to be determined and added to the synchronisation error.

You need a lot of creativity to find a good solution, because you have
to deal with reality. The book shows just a concept, but not the
solution.

Have a nice synthesis
Eilert